68 lines
2.6 KiB
YAML
68 lines
2.6 KiB
YAML
# RUN: llc -O1 -start-after register-coalescer -o - %s -experimental-debug-variable-locations=true | FileCheck %s
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--- |
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-pc-linux-gnu"
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define i16 @foo(i8 %zzz) !dbg !4 {
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entry:
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ret i16 1
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}
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; Function Attrs: nounwind readnone speculatable
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declare void @llvm.dbg.value(metadata, metadata, metadata)
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!3}
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!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2)
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!1 = !DIFile(filename: "test.c", directory: "")
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!2 = !{}
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!3 = !{i32 1, !"Debug Info Version", i32 3}
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!4 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !0)
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!5 = !DISubroutineType(types: !6)
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!6 = !{null}
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!7 = !DILocalVariable(name: "zzz", arg: 1, scope: !4, file: !1, line: 3, type: !8)
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!8 = !DIBasicType(name: "char", size: 8, align: 8, encoding: DW_ATE_signed)
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!9 = !DILocation(line: 0, scope: !4)
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!10 = !DILocation(line: 4, column: 22, scope: !11)
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!11 = distinct !DILexicalBlock(scope: !4, file: !1, line: 3, column: 19)
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...
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---
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name: foo
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tracksRegLiveness: true
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debugInstrRef: true
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debugValueSubstitutions:
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- { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 2 }
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body: |
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bb.0:
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%0:gr16_abcd = MOV16ri 1, debug-instr-number 1, debug-location !9
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bb.1:
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DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0), debug-location !9
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%1:gr16 = COPY %0, debug-location !9
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%2:gr16 = COPY %0
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bb.2:
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$ax = COPY %1, debug-location !9
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$dx = COPY %2
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RET64 killed $ax, killed $dx, debug-location !9
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...
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# This test is an instruction-referencing flavour of the
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# dbg-value-superreg-copy.mir test. Over there, we ran into difficulties where
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# register coalescing would transform DBG_VALUEs of subregisters such as:
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#
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# DBG_VALUE %0.sub_8bit_hi, $noreg,
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#
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# Into references to larger registers, potentially with the wrong offset. We
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# can't refer to vregs in instruction referencing mode, so this test replicates
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# the same scenario in a new test. The defining storing load gets an instruction
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# number, and we encode which subregister we want through a substitution. Check
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# that it comes out the other end of regalloc through coalescing still in a
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# high register.
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#
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# CHECK-NOT: #DEBUG_VALUE:
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# CHECK: #DEBUG_VALUE: foo:zzz <- ${{[abcd]+}}h
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# CHECK-NOT: #DEBUG_VALUE:
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