82 lines
2.9 KiB
ArmAsm
82 lines
2.9 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Registers list not in ascending order
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zero {za1.s, za0.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: warning: tile list not in ascending order
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// CHECK-NEXT: zero {za1.s, za0.s}
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// CHECK-NEXT: ^
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zero {za0.d, za1.d, za4.d, za3.d}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: warning: tile list not in ascending order
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// CHECK-NEXT: zero {za0.d, za1.d, za4.d, za3.d}
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// CHECK-NEXT: ^
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// --------------------------------------------------------------------------//
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// Duplicate tile
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zero {za0.s, za0.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: warning: duplicate tile in list
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// CHECK-NEXT: zero {za0.s, za0.s}
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// CHECK-NEXT: ^
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zero {za0.d, za1.d, za2.d, za2.d, za3.d}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: warning: duplicate tile in list
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// CHECK-NEXT: zero {za0.d, za1.d, za2.d, za2.d, za3.d}
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// CHECK-NEXT: ^
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// --------------------------------------------------------------------------//
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// Mismatched register size suffix
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zero {za0.b, za5.d}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
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// CHECK-NEXT: zero {za0.b, za5.d}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Missing '}'
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zero {za
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: '}' expected
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// CHECK-NEXT: zero {za
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// CHECK-NEXT: ^
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid matrix tile
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zero {za0.b, za1.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zero {za0.b, za1.b}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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zero {za2.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zero {za2.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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zero {za0.s, za1.s, za2.s, za3.s, za4.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zero {za0.s, za1.s, za2.s, za3.s, za4.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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zero {za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d, za8.d}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zero {za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d, za8.d}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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zero {za0h.b}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zero {za0h.b}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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zero {za0.s, za1h.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zero {za0.s, za1h.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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zero {za15.q}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: zero {za15.q}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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