27 lines
1.1 KiB
ArmAsm
27 lines
1.1 KiB
ArmAsm
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid vector list
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scvtf {z0.s-z3.s}, {z0.s-z4.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: scvtf {z0.s-z3.s}, {z0.s-z4.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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scvtf {z1.s-z2.s}, {z0.s-z1.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: scvtf {z1.s-z2.s}, {z0.s-z1.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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scvtf {z0.s-z3.s}, {z1.s-z5.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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// CHECK-NEXT: scvtf {z0.s-z3.s}, {z1.s-z5.s}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid Register Suffix
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scvtf {z0.s-z3.s}, {z1.h-z3.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: scvtf {z0.s-z3.s}, {z1.h-z3.h}
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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