bolt/deps/llvm-18.1.8/llvm/test/MC/AArch64/SVE/pfalse-diagnostics.s
2025-02-14 19:21:04 +01:00

22 lines
702 B
ArmAsm

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Only .b is supported
pfalse p15.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: pfalse p15.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Support until pn15.b
pfalse pn16.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: pfalse pn16.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
pfalse pn5.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Expected predicate-as-counter register name with .B suffix
// CHECK-NEXT: pfalse pn5.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: