bolt/deps/llvm-18.1.8/llvm/test/MC/AArch64/SVE2/whilewr-diagnostics.s
2025-02-14 19:21:04 +01:00

25 lines
895 B
ArmAsm

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid scalar registers
whilewr p15.b, xzr, sp
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, xzr, sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilewr p15.b, xzr, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, xzr, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilewr p15.b, w0, x0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, w0, x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
whilewr p15.b, w0, w0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: whilewr p15.b, w0, w0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: