1151 lines
29 KiB
ArmAsm
1151 lines
29 KiB
ArmAsm
# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
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# RUN: | llvm-objdump -d - \
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# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
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######################################
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# Machine Trap Setup
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######################################
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# mstatush
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# name
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# CHECK-INST: csrrs t1, mstatush, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x00,0x31]
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# CHECK-INST-ALIAS: csrr t1, mstatush
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# uimm12
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# CHECK-INST: csrrs t2, mstatush, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x31]
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# CHECK-INST-ALIAS: csrr t2, mstatush
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# name
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csrrs t1, mstatush, zero
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# uimm12
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csrrs t2, 0x310, zero
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#########################
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# Machine Configuration
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#########################
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# menvcfgh
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# name
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# CHECK-INST: csrrs t1, menvcfgh, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x31]
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# CHECK-INST-ALIAS: csrr t1, menvcfgh
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# uimm12
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# CHECK-INST: csrrs t2, menvcfgh, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x31]
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# CHECK-INST-ALIAS: csrr t2, menvcfgh
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# name
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csrrs t1, menvcfgh, zero
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# uimm12
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csrrs t2, 0x31A, zero
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# mseccfgh
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# name
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# CHECK-INST: csrrs t1, mseccfgh, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x70,0x75]
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# CHECK-INST-ALIAS: csrr t1, mseccfgh
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# uimm12
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# CHECK-INST: csrrs t2, mseccfgh, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x75]
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# CHECK-INST-ALIAS: csrr t2, mseccfgh
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# name
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csrrs t1, mseccfgh, zero
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# uimm12
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csrrs t2, 0x757, zero
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######################################
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# Machine Protection and Translation
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######################################
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# pmpcfg1
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# name
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# CHECK-INST: csrrs t1, pmpcfg1, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x10,0x3a]
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# CHECK-INST-ALIAS: csrr t1, pmpcfg1
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# uimm12
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# CHECK-INST: csrrs t2, pmpcfg1, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x3a]
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# CHECK-INST-ALIAS: csrr t2, pmpcfg1
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# name
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csrrs t1, pmpcfg1, zero
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# uimm12
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csrrs t2, 0x3A1, zero
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# pmpcfg3
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# name
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# CHECK-INST: csrrs t1, pmpcfg3, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x30,0x3a]
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# CHECK-INST-ALIAS: csrr t1, pmpcfg3
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# uimm12
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# CHECK-INST: csrrs t2, pmpcfg3, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x3a]
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# CHECK-INST-ALIAS: csrr t2, pmpcfg3
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# name
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csrrs t1, pmpcfg3, zero
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# uimm12
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csrrs t2, 0x3A3, zero
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# pmpcfg5
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# name
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# CHECK-INST: csrrs t1, pmpcfg5, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x50,0x3a]
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# CHECK-INST-ALIAS: csrr t1, pmpcfg5
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# uimm12
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# CHECK-INST: csrrs t2, pmpcfg5, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x3a]
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# CHECK-INST-ALIAS: csrr t2, pmpcfg5
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# name
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csrrs t1, pmpcfg5, zero
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# uimm12
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csrrs t2, 0x3A5, zero
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# pmpcfg7
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# name
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# CHECK-INST: csrrs t1, pmpcfg7, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x70,0x3a]
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# CHECK-INST-ALIAS: csrr t1, pmpcfg7
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# uimm12
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# CHECK-INST: csrrs t2, pmpcfg7, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x3a]
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# CHECK-INST-ALIAS: csrr t2, pmpcfg7
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# name
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csrrs t1, pmpcfg7, zero
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# uimm12
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csrrs t2, 0x3A7, zero
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# pmpcfg9
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# name
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# CHECK-INST: csrrs t1, pmpcfg9, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x90,0x3a]
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# CHECK-INST-ALIAS: csrr t1, pmpcfg9
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# uimm12
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# CHECK-INST: csrrs t2, pmpcfg9, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x3a]
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# CHECK-INST-ALIAS: csrr t2, pmpcfg9
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# name
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csrrs t1, pmpcfg9, zero
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# uimm12
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csrrs t2, 0x3A9, zero
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# pmpcfg11
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# name
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# CHECK-INST: csrrs t1, pmpcfg11, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xb0,0x3a]
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# CHECK-INST-ALIAS: csrr t1, pmpcfg11
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# uimm12
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# CHECK-INST: csrrs t2, pmpcfg11, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xb0,0x3a]
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# CHECK-INST-ALIAS: csrr t2, pmpcfg11
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# name
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csrrs t1, pmpcfg11, zero
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# uimm12
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csrrs t2, 0x3AB, zero
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# pmpcfg13
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# name
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# CHECK-INST: csrrs t1, pmpcfg13, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x3a]
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# CHECK-INST-ALIAS: csrr t1, pmpcfg13
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# uimm12
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# CHECK-INST: csrrs t2, pmpcfg13, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x3a]
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# CHECK-INST-ALIAS: csrr t2, pmpcfg13
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# name
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csrrs t1, pmpcfg13, zero
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# uimm12
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csrrs t2, 0x3AD, zero
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# pmpcfg15
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# name
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# CHECK-INST: csrrs t1, pmpcfg15, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x3a]
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# CHECK-INST-ALIAS: csrr t1, pmpcfg15
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# uimm12
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# CHECK-INST: csrrs t2, pmpcfg15, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x3a]
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# CHECK-INST-ALIAS: csrr t2, pmpcfg15
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# name
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csrrs t1, pmpcfg15, zero
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# uimm12
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csrrs t2, 0x3AF, zero
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######################################
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# Machine Counter and Timers
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######################################
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# mcycleh
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# name
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# CHECK-INST: csrrs t1, mcycleh, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x00,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mcycleh
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# uimm12
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# CHECK-INST: csrrs t2, mcycleh, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mcycleh
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csrrs t1, mcycleh, zero
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# uimm12
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csrrs t2, 0xB80, zero
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# minstreth
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# name
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# CHECK-INST: csrrs t1, minstreth, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x20,0xb8]
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# CHECK-INST-ALIAS: csrr t1, minstreth
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# uimm12
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# CHECK-INST: csrrs t2, minstreth, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x20,0xb8]
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# CHECK-INST-ALIAS: csrr t2, minstreth
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# name
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csrrs t1, minstreth, zero
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# uimm12
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csrrs t2, 0xB82, zero
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# mhpmcounter3h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter3h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x30,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter3h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter3h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x30,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter3h
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# name
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csrrs t1, mhpmcounter3h, zero
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# uimm12
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csrrs t2, 0xB83, zero
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# mhpmcounter4h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter4h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x40,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter4h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter4h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x40,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter4h
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# name
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csrrs t1, mhpmcounter4h, zero
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# uimm12
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csrrs t2, 0xB84, zero
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# mhpmcounter5h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter5h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x50,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter5h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter5h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x50,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter5h
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# name
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csrrs t1, mhpmcounter5h, zero
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# uimm12
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csrrs t2, 0xB85, zero
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# mhpmcounter6h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter6h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x60,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter6h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter6h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x60,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter6h
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# name
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csrrs t1, mhpmcounter6h, zero
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# uimm12
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csrrs t2, 0xB86, zero
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# mhpmcounter7h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter7h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x70,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter7h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter7h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x70,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter7h
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# name
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csrrs t1, mhpmcounter7h, zero
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# uimm12
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csrrs t2, 0xB87, zero
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# mhpmcounter8h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter8h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x80,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter8h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter8h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x80,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter8h
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# name
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csrrs t1, mhpmcounter8h, zero
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# uimm12
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csrrs t2, 0xB88, zero
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# mhpmcounter9h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter9h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x90,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter9h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter9h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x90,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter9h
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# name
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csrrs t1, mhpmcounter9h, zero
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# uimm12
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csrrs t2, 0xB89, zero
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# mhpmcounter10h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter10h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xa0,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter10h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter10h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter10h
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# name
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csrrs t1, mhpmcounter10h, zero
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# uimm12
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csrrs t2, 0xB8A, zero
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# mhpmcounter11h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter11h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xb0,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter11h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter11h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xb0,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter11h
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# name
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csrrs t1, mhpmcounter11h, zero
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# uimm12
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csrrs t2, 0xB8B, zero
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# mhpmcounter12h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter12h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xc0,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter12h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter12h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter12h
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# name
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csrrs t1, mhpmcounter12h, zero
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# uimm12
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csrrs t2, 0xB8C, zero
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# mhpmcounter13h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter13h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xd0,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter13h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter13h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter13h
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# name
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csrrs t1, mhpmcounter13h, zero
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# uimm12
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csrrs t2, 0xB8D, zero
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# mhpmcounter14h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter14h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xe0,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter14h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter14h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter14h
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# name
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csrrs t1, mhpmcounter14h, zero
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# uimm12
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csrrs t2, 0xB8E, zero
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# mhpmcounter15h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter15h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0xf0,0xb8]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter15h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter15h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0xb8]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter15h
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# name
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csrrs t1, mhpmcounter15h, zero
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# uimm12
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csrrs t2, 0xB8F, zero
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# mhpmcounter16h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter16h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x00,0xb9]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter16h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter16h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xb9]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter16h
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# name
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csrrs t1, mhpmcounter16h, zero
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# uimm12
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csrrs t2, 0xB90, zero
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# mhpmcounter17h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter17h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x10,0xb9]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter17h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter17h, zero
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# CHECK-ENC: encoding: [0xf3,0x23,0x10,0xb9]
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# CHECK-INST-ALIAS: csrr t2, mhpmcounter17h
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# name
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csrrs t1, mhpmcounter17h, zero
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# uimm12
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csrrs t2, 0xB91, zero
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# mhpmcounter18h
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# name
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# CHECK-INST: csrrs t1, mhpmcounter18h, zero
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# CHECK-ENC: encoding: [0x73,0x23,0x20,0xb9]
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# CHECK-INST-ALIAS: csrr t1, mhpmcounter18h
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# uimm12
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# CHECK-INST: csrrs t2, mhpmcounter18h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter18h
|
|
# name
|
|
csrrs t1, mhpmcounter18h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB92, zero
|
|
|
|
# mhpmcounter19h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter19h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x30,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter19h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter19h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter19h
|
|
# name
|
|
csrrs t1, mhpmcounter19h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB93, zero
|
|
|
|
# mhpmcounter20h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter20h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x40,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter20h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter20h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter20h
|
|
# name
|
|
csrrs t1, mhpmcounter20h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB94, zero
|
|
|
|
# mhpmcounter21h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter21h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x50,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter21h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter21h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x50,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter21h
|
|
# name
|
|
csrrs t1, mhpmcounter21h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB95, zero
|
|
|
|
# mhpmcounter22h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter22h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x60,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter22h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter22h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x60,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter22h
|
|
# name
|
|
csrrs t1, mhpmcounter22h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB96, zero
|
|
|
|
# mhpmcounter23h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter23h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x70,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter23h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter23h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x70,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter23h
|
|
# name
|
|
csrrs t1, mhpmcounter23h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB97, zero
|
|
|
|
# mhpmcounter24h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter24h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x80,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter24h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter24h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x80,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter24h
|
|
# name
|
|
csrrs t1, mhpmcounter24h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB98, zero
|
|
|
|
# mhpmcounter25h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter25h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x90,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter25h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter25h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x90,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter25h
|
|
# name
|
|
csrrs t1, mhpmcounter25h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB99, zero
|
|
|
|
# mhpmcounter26h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter26h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xa0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter26h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter26h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter26h
|
|
# name
|
|
csrrs t1, mhpmcounter26h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB9A, zero
|
|
|
|
# mhpmcounter27h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter27h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xb0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter27h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter27h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xb0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter27h
|
|
# name
|
|
csrrs t1, mhpmcounter27h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB9B, zero
|
|
|
|
# mhpmcounter28h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter28h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xc0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter28h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter28h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter28h
|
|
# name
|
|
csrrs t1, mhpmcounter28h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB9C, zero
|
|
|
|
# mhpmcounter29h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter29h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xd0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter29h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter29h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter29h
|
|
# name
|
|
csrrs t1, mhpmcounter29h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB9D, zero
|
|
|
|
# mhpmcounter30h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter30h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xe0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter30h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter30h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter30h
|
|
# name
|
|
csrrs t1, mhpmcounter30h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB9E, zero
|
|
|
|
# mhpmcounter31h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmcounter31h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xf0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmcounter31h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmcounter31h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0xb9]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmcounter31h
|
|
# name
|
|
csrrs t1, mhpmcounter31h, zero
|
|
# uimm12
|
|
csrrs t2, 0xB9F, zero
|
|
|
|
######################################
|
|
# Machine Counter Setup
|
|
######################################
|
|
|
|
# mhpmevent3h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent3h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent3h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent3h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent3h
|
|
# name
|
|
csrrs t1, mhpmevent3h, zero
|
|
# uimm12
|
|
csrrs t2, 0x723, zero
|
|
|
|
# mhpmevent4h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent4h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x40,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent4h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent4h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent4h
|
|
# name
|
|
csrrs t1, mhpmevent4h, zero
|
|
# uimm12
|
|
csrrs t2, 0x724, zero
|
|
|
|
# mhpmevent5h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent5h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x50,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent5h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent5h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent5h
|
|
# name
|
|
csrrs t1, mhpmevent5h, zero
|
|
# uimm12
|
|
csrrs t2, 0x725, zero
|
|
|
|
# mhpmevent6h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent6h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x60,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent6h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent6h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent6h
|
|
# name
|
|
csrrs t1, mhpmevent6h, zero
|
|
# uimm12
|
|
csrrs t2, 0x726, zero
|
|
|
|
# mhpmevent7h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent7h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x70,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent7h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent7h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent7h
|
|
# name
|
|
csrrs t1, mhpmevent7h, zero
|
|
# uimm12
|
|
csrrs t2, 0x727, zero
|
|
|
|
# mhpmevent8h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent8h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x80,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent8h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent8h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent8h
|
|
# name
|
|
csrrs t1, mhpmevent8h, zero
|
|
# uimm12
|
|
csrrs t2, 0x728, zero
|
|
|
|
# mhpmevent9h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent9h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x90,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent9h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent9h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent9h
|
|
# name
|
|
csrrs t1, mhpmevent9h, zero
|
|
# uimm12
|
|
csrrs t2, 0x729, zero
|
|
|
|
# mhpmevent10h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent10h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent10h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent10h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent10h
|
|
# name
|
|
csrrs t1, mhpmevent10h, zero
|
|
# uimm12
|
|
csrrs t2, 0x72a, zero
|
|
|
|
# mhpmevent11h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent11h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xb0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent11h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent11h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xb0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent11h
|
|
# name
|
|
csrrs t1, mhpmevent11h, zero
|
|
# uimm12
|
|
csrrs t2, 0x72B, zero
|
|
|
|
# mhpmevent12h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent12h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent12h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent12h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent12h
|
|
# name
|
|
csrrs t1, mhpmevent12h, zero
|
|
# uimm12
|
|
csrrs t2, 0x72C, zero
|
|
|
|
# mhpmevent13h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent13h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent13h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent13h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent13h
|
|
# name
|
|
csrrs t1, mhpmevent13h, zero
|
|
# uimm12
|
|
csrrs t2, 0x72D, zero
|
|
|
|
# mhpmevent14h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent14h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent14h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent14h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent14h
|
|
# name
|
|
csrrs t1, mhpmevent14h, zero
|
|
# uimm12
|
|
csrrs t2, 0x72E, zero
|
|
|
|
# mhpmevent15h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent15h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent15h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent15h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x72]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent15h
|
|
# name
|
|
csrrs t1, mhpmevent15h, zero
|
|
# uimm12
|
|
csrrs t2, 0x72F, zero
|
|
|
|
# mhpmevent16h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent16h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent16h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent16h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent16h
|
|
# name
|
|
csrrs t1, mhpmevent16h, zero
|
|
# uimm12
|
|
csrrs t2, 0x730, zero
|
|
|
|
# mhpmevent17h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent17h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x10,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent17h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent17h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent17h
|
|
# name
|
|
csrrs t1, mhpmevent17h, zero
|
|
# uimm12
|
|
csrrs t2, 0x731, zero
|
|
|
|
# mhpmevent18h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent18h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x20,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent18h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent18h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent18h
|
|
# name
|
|
csrrs t1, mhpmevent18h, zero
|
|
# uimm12
|
|
csrrs t2, 0x732, zero
|
|
|
|
# mhpmevent19h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent19h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent19h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent19h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent19h
|
|
# name
|
|
csrrs t1, mhpmevent19h, zero
|
|
# uimm12
|
|
csrrs t2, 0x733, zero
|
|
|
|
# mhpmevent20h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent20h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x40,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent20h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent20h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent20h
|
|
# name
|
|
csrrs t1, mhpmevent20h, zero
|
|
# uimm12
|
|
csrrs t2, 0x734, zero
|
|
|
|
# mhpmevent21h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent21h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x50,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent21h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent21h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent21h
|
|
# name
|
|
csrrs t1, mhpmevent21h, zero
|
|
# uimm12
|
|
csrrs t2, 0x735, zero
|
|
|
|
# mhpmevent22h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent22h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x60,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent22h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent22h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent22h
|
|
# name
|
|
csrrs t1, mhpmevent22h, zero
|
|
# uimm12
|
|
csrrs t2, 0x736, zero
|
|
|
|
# mhpmevent23h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent23h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x70,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent23h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent23h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent23h
|
|
# name
|
|
csrrs t1, mhpmevent23h, zero
|
|
# uimm12
|
|
csrrs t2, 0x737, zero
|
|
|
|
# mhpmevent24h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent24h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x80,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent24h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent24h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent24h
|
|
# name
|
|
csrrs t1, mhpmevent24h, zero
|
|
# uimm12
|
|
csrrs t2, 0x738, zero
|
|
|
|
# mhpmevent25h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent25h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x90,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent25h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent25h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent25h
|
|
# name
|
|
csrrs t1, mhpmevent25h, zero
|
|
# uimm12
|
|
csrrs t2, 0x739, zero
|
|
|
|
# mhpmevent26h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent26h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent26h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent26h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent26h
|
|
# name
|
|
csrrs t1, mhpmevent26h, zero
|
|
# uimm12
|
|
csrrs t2, 0x73A, zero
|
|
|
|
# mhpmevent27h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent27h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xb0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent27h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent27h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xb0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent27h
|
|
# name
|
|
csrrs t1, mhpmevent27h, zero
|
|
# uimm12
|
|
csrrs t2, 0x73B, zero
|
|
|
|
# mhpmevent28h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent28h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent28h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent28h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent28h
|
|
# name
|
|
csrrs t1, mhpmevent28h, zero
|
|
# uimm12
|
|
csrrs t2, 0x73C, zero
|
|
|
|
# mhpmevent29h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent29h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent29h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent29h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent29h
|
|
# name
|
|
csrrs t1, mhpmevent29h, zero
|
|
# uimm12
|
|
csrrs t2, 0x73D, zero
|
|
|
|
# mhpmevent30h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent30h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent30h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent30h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent30h
|
|
# name
|
|
csrrs t1, mhpmevent30h, zero
|
|
# uimm12
|
|
csrrs t2, 0x73E, zero
|
|
|
|
# mhpmevent31h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mhpmevent31h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t1, mhpmevent31h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mhpmevent31h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x73]
|
|
# CHECK-INST-ALIAS: csrr t2, mhpmevent31h
|
|
# name
|
|
csrrs t1, mhpmevent31h, zero
|
|
# uimm12
|
|
csrrs t2, 0x73F, zero
|
|
|
|
#########################################
|
|
# State Enable Extension (Smstateen)
|
|
#########################################
|
|
|
|
# mstateen0h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mstateen0h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x31]
|
|
# CHECK-INST-ALIAS: csrr t1, mstateen0h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mstateen0h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x31]
|
|
# CHECK-INST-ALIAS: csrr t2, mstateen0h
|
|
# name
|
|
csrrs t1, mstateen0h, zero
|
|
# uimm12
|
|
csrrs t2, 0x31C, zero
|
|
|
|
# mstateen1h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mstateen1h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x31]
|
|
# CHECK-INST-ALIAS: csrr t1, mstateen1h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mstateen1h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x31]
|
|
# CHECK-INST-ALIAS: csrr t2, mstateen1h
|
|
# name
|
|
csrrs t1, mstateen1h, zero
|
|
# uimm12
|
|
csrrs t2, 0x31D, zero
|
|
|
|
# mstateen2h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mstateen2h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x31]
|
|
# CHECK-INST-ALIAS: csrr t1, mstateen2h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mstateen2h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x31]
|
|
# CHECK-INST-ALIAS: csrr t2, mstateen2h
|
|
# name
|
|
csrrs t1, mstateen2h, zero
|
|
# uimm12
|
|
csrrs t2, 0x31E, zero
|
|
|
|
# mstateen3h
|
|
# name
|
|
# CHECK-INST: csrrs t1, mstateen3h, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x31]
|
|
# CHECK-INST-ALIAS: csrr t1, mstateen3h
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mstateen3h, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x31]
|
|
# CHECK-INST-ALIAS: csrr t2, mstateen3h
|
|
# name
|
|
csrrs t1, mstateen3h, zero
|
|
# uimm12
|
|
csrrs t2, 0x31F, zero
|
|
|
|
#########################################
|
|
# Advanced Interrupt Architecture (Smaia and Ssaia)
|
|
#########################################
|
|
|
|
# midelegh
|
|
# name
|
|
# CHECK-INST: csrrs t1, midelegh, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x30,0x31]
|
|
# CHECK-INST-ALIAS: csrr t1, midelegh
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, midelegh, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x31]
|
|
# CHECK-INST-ALIAS: csrr t2, midelegh
|
|
# name
|
|
csrrs t1, midelegh, zero
|
|
# uimm12
|
|
csrrs t2, 0x313, zero
|
|
|
|
# mieh
|
|
# name
|
|
# CHECK-INST: csrrs t1, mieh, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x40,0x31]
|
|
# CHECK-INST-ALIAS: csrr t1, mieh
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mieh, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x31]
|
|
# CHECK-INST-ALIAS: csrr t2, mieh
|
|
# name
|
|
csrrs t1, mieh, zero
|
|
# uimm12
|
|
csrrs t2, 0x314, zero
|
|
|
|
# mvienh
|
|
# name
|
|
# CHECK-INST: csrrs t1, mvienh, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x80,0x31]
|
|
# CHECK-INST-ALIAS: csrr t1, mvienh
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mvienh, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x31]
|
|
# CHECK-INST-ALIAS: csrr t2, mvienh
|
|
# name
|
|
csrrs t1, mvienh, zero
|
|
# uimm12
|
|
csrrs t2, 0x318, zero
|
|
|
|
# mviph
|
|
# name
|
|
# CHECK-INST: csrrs t1, mviph, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x90,0x31]
|
|
# CHECK-INST-ALIAS: csrr t1, mviph
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, mviph, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x31]
|
|
# CHECK-INST-ALIAS: csrr t2, mviph
|
|
# name
|
|
csrrs t1, mviph, zero
|
|
# uimm12
|
|
csrrs t2, 0x319, zero
|
|
|
|
# miph
|
|
# name
|
|
# CHECK-INST: csrrs t1, miph, zero
|
|
# CHECK-ENC: encoding: [0x73,0x23,0x40,0x35]
|
|
# CHECK-INST-ALIAS: csrr t1, miph
|
|
# uimm12
|
|
# CHECK-INST: csrrs t2, miph, zero
|
|
# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x35]
|
|
# CHECK-INST-ALIAS: csrr t2, miph
|
|
# name
|
|
csrrs t1, miph, zero
|
|
# uimm12
|
|
csrrs t2, 0x354, zero
|