42 lines
2.1 KiB
ArmAsm
42 lines
2.1 KiB
ArmAsm
# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
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# RUN: | llvm-objdump --mattr=+a -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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#
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# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
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# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
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# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
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# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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lr.d t0, (t1)
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# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
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# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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lr.d.aq t1, (t2)
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# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
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# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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lr.d.rl t2, (t3)
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# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
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# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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lr.d.aqrl t3, (t4)
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# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
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# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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sc.d t6, t5, (t4)
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# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
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# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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sc.d.aq t5, t4, (t3)
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# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
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# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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sc.d.rl t4, t3, (t2)
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# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
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# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
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# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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sc.d.aqrl t3, t2, (t1)
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