337 lines
11 KiB
LLVM
337 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=indvars < %s | FileCheck %s
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; Check that we replace signed comparisons between non-negative values with
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; unsigned comparisons if we can.
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target datalayout = "n8:16:32:64"
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define i32 @test_01(i32 %a, i32 %b, ptr %p) {
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; CHECK-LABEL: @test_01(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP_ENTRY:%.*]]
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; CHECK: loop.entry:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_BE:%.*]] ]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i32 [[IV]], 100
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; CHECK-NEXT: br i1 [[CMP1]], label [[B1:%.*]], label [[B2:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: store i32 [[IV]], ptr [[P:%.*]], align 4
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; CHECK-NEXT: br label [[MERGE:%.*]]
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; CHECK: b2:
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; CHECK-NEXT: store i32 [[A:%.*]], ptr [[P]], align 4
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; CHECK-NEXT: br label [[MERGE]]
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; CHECK: merge:
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i32 [[IV]], 100
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; CHECK-NEXT: br i1 [[CMP2]], label [[B3:%.*]], label [[B4:%.*]]
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; CHECK: b3:
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; CHECK-NEXT: store i32 [[IV]], ptr [[P]], align 4
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; CHECK-NEXT: br label [[LOOP_BE]]
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; CHECK: b4:
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; CHECK-NEXT: store i32 [[B:%.*]], ptr [[P]], align 4
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; CHECK-NEXT: br label [[LOOP_BE]]
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; CHECK: loop.be:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV_NEXT]], 1000
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP_ENTRY]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 999
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;
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entry:
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br label %loop.entry
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loop.entry:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.be ]
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%cmp1 = icmp slt i32 %iv, 100
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br i1 %cmp1, label %b1, label %b2
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b1:
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store i32 %iv, ptr %p
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br label %merge
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b2:
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store i32 %a, ptr %p
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br label %merge
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merge:
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%cmp2 = icmp ult i32 %iv, 100
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br i1 %cmp2, label %b3, label %b4
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b3:
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store i32 %iv, ptr %p
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br label %loop.be
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b4:
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store i32 %b, ptr %p
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br label %loop.be
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loop.be:
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%iv.next = add i32 %iv, 1
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%cmp3 = icmp slt i32 %iv.next, 1000
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br i1 %cmp3, label %loop.entry, label %exit
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exit:
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ret i32 %iv
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}
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define i32 @test_02(i32 %a, i32 %b, ptr %p) {
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; CHECK-LABEL: @test_02(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP_ENTRY:%.*]]
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; CHECK: loop.entry:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_BE:%.*]] ]
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ugt i32 100, [[IV]]
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; CHECK-NEXT: br i1 [[CMP1]], label [[B1:%.*]], label [[B2:%.*]]
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; CHECK: b1:
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; CHECK-NEXT: store i32 [[IV]], ptr [[P:%.*]], align 4
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; CHECK-NEXT: br label [[MERGE:%.*]]
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; CHECK: b2:
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; CHECK-NEXT: store i32 [[A:%.*]], ptr [[P]], align 4
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; CHECK-NEXT: br label [[MERGE]]
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; CHECK: merge:
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt i32 100, [[IV]]
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; CHECK-NEXT: br i1 [[CMP2]], label [[B3:%.*]], label [[B4:%.*]]
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; CHECK: b3:
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; CHECK-NEXT: store i32 [[IV]], ptr [[P]], align 4
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; CHECK-NEXT: br label [[LOOP_BE]]
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; CHECK: b4:
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; CHECK-NEXT: store i32 [[B:%.*]], ptr [[P]], align 4
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; CHECK-NEXT: br label [[LOOP_BE]]
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; CHECK: loop.be:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV_NEXT]], 1000
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP_ENTRY]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 999
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;
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entry:
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br label %loop.entry
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loop.entry:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.be ]
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%cmp1 = icmp sgt i32 100, %iv
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br i1 %cmp1, label %b1, label %b2
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b1:
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store i32 %iv, ptr %p
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br label %merge
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b2:
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store i32 %a, ptr %p
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br label %merge
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merge:
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%cmp2 = icmp ugt i32 100, %iv
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br i1 %cmp2, label %b3, label %b4
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b3:
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store i32 %iv, ptr %p
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br label %loop.be
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b4:
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store i32 %b, ptr %p
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br label %loop.be
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loop.be:
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%iv.next = add i32 %iv, 1
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%cmp3 = icmp sgt i32 1000, %iv.next
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br i1 %cmp3, label %loop.entry, label %exit
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exit:
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ret i32 %iv
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}
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define i32 @test_03(ptr %p, ptr %capacity_p, ptr %num_elements_p) {
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; CHECK-LABEL: @test_03(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CAPACITY:%.*]] = load i32, ptr [[CAPACITY_P:%.*]], align 4, !range [[RNG0:![0-9]+]]
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; CHECK-NEXT: [[NUM_ELEMENTS:%.*]] = load i32, ptr [[NUM_ELEMENTS_P:%.*]], align 4, !range [[RNG0]]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
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; CHECK-NEXT: [[BYTES_TO_WRITE:%.*]] = sub nuw nsw i32 [[CAPACITY]], [[IV]]
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; CHECK-NEXT: [[CAPACITY_CHECK:%.*]] = icmp slt i32 [[BYTES_TO_WRITE]], 4
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; CHECK-NEXT: br i1 [[CAPACITY_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P:%.*]], i32 [[IV]]
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; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
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; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[NUM_ELEMENTS]]
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
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; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
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; CHECK: out_of_bounds:
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; CHECK-NEXT: ret i32 -1
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;
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entry:
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%capacity = load i32, ptr %capacity_p, !range !0
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%num_elements = load i32, ptr %num_elements_p, !range !0
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %backedge]
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%bytes_to_write = sub i32 %capacity, %iv
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%capacity_check = icmp slt i32 %bytes_to_write, 4
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br i1 %capacity_check, label %out_of_bounds, label %backedge
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backedge:
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%el.ptr = getelementptr i32, ptr %p, i32 %iv
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store i32 1, ptr %el.ptr
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%iv.next = add nuw nsw i32 %iv, 4
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%loop_cond = icmp slt i32 %iv.next, %num_elements
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv.next
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out_of_bounds:
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ret i32 -1
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}
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define i32 @test_04(ptr %p, ptr %capacity_p, ptr %num_elements_p) {
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; CHECK-LABEL: @test_04(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CAPACITY:%.*]] = load i32, ptr [[CAPACITY_P:%.*]], align 4, !range [[RNG0]]
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; CHECK-NEXT: [[NUM_ELEMENTS:%.*]] = load i32, ptr [[NUM_ELEMENTS_P:%.*]], align 4, !range [[RNG0]]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
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; CHECK-NEXT: [[BYTES_TO_WRITE:%.*]] = sub nuw nsw i32 [[CAPACITY]], [[IV]]
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; CHECK-NEXT: [[CAPACITY_CHECK:%.*]] = icmp sle i32 [[BYTES_TO_WRITE]], 3
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; CHECK-NEXT: br i1 [[CAPACITY_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P:%.*]], i32 [[IV]]
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; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
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; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[NUM_ELEMENTS]]
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
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; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
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; CHECK: out_of_bounds:
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; CHECK-NEXT: ret i32 -1
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;
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entry:
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%capacity = load i32, ptr %capacity_p, !range !0
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%num_elements = load i32, ptr %num_elements_p, !range !0
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %backedge]
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%bytes_to_write = sub i32 %capacity, %iv
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%capacity_check = icmp sle i32 %bytes_to_write, 3
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br i1 %capacity_check, label %out_of_bounds, label %backedge
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backedge:
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%el.ptr = getelementptr i32, ptr %p, i32 %iv
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store i32 1, ptr %el.ptr
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%iv.next = add nuw nsw i32 %iv, 4
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%loop_cond = icmp slt i32 %iv.next, %num_elements
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv.next
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out_of_bounds:
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ret i32 -1
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}
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define i32 @test_05(ptr %p, ptr %capacity_p, ptr %num_elements_p) {
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; CHECK-LABEL: @test_05(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CAPACITY:%.*]] = load i32, ptr [[CAPACITY_P:%.*]], align 4, !range [[RNG0]]
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; CHECK-NEXT: [[NUM_ELEMENTS:%.*]] = load i32, ptr [[NUM_ELEMENTS_P:%.*]], align 4, !range [[RNG0]]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
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; CHECK-NEXT: [[BYTES_TO_WRITE:%.*]] = sub nuw nsw i32 [[CAPACITY]], [[IV]]
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; CHECK-NEXT: [[CAPACITY_CHECK:%.*]] = icmp ult i32 [[BYTES_TO_WRITE]], 4
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; CHECK-NEXT: br i1 [[CAPACITY_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P:%.*]], i32 [[IV]]
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; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
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; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[NUM_ELEMENTS]]
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
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; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
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; CHECK: out_of_bounds:
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; CHECK-NEXT: ret i32 -1
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;
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entry:
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%capacity = load i32, ptr %capacity_p, !range !0
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%num_elements = load i32, ptr %num_elements_p, !range !0
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %backedge]
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%bytes_to_write = sub i32 %capacity, %iv
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%capacity_check = icmp ult i32 %bytes_to_write, 4
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br i1 %capacity_check, label %out_of_bounds, label %backedge
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backedge:
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%el.ptr = getelementptr i32, ptr %p, i32 %iv
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store i32 1, ptr %el.ptr
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%iv.next = add nuw nsw i32 %iv, 4
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%loop_cond = icmp slt i32 %iv.next, %num_elements
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv.next
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out_of_bounds:
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ret i32 -1
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}
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define i32 @test_06(ptr %p, ptr %capacity_p, ptr %num_elements_p) {
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; CHECK-LABEL: @test_06(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CAPACITY:%.*]] = load i32, ptr [[CAPACITY_P:%.*]], align 4, !range [[RNG0]]
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; CHECK-NEXT: [[NUM_ELEMENTS:%.*]] = load i32, ptr [[NUM_ELEMENTS_P:%.*]], align 4, !range [[RNG0]]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
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; CHECK-NEXT: [[BYTES_TO_WRITE:%.*]] = sub nuw nsw i32 [[CAPACITY]], [[IV]]
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; CHECK-NEXT: [[CAPACITY_CHECK:%.*]] = icmp ule i32 [[BYTES_TO_WRITE]], 3
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; CHECK-NEXT: br i1 [[CAPACITY_CHECK]], label [[OUT_OF_BOUNDS:%.*]], label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[EL_PTR:%.*]] = getelementptr i32, ptr [[P:%.*]], i32 [[IV]]
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; CHECK-NEXT: store i32 1, ptr [[EL_PTR]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 4
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; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[IV_NEXT]], [[NUM_ELEMENTS]]
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: [[IV_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_NEXT]], [[BACKEDGE]] ]
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; CHECK-NEXT: ret i32 [[IV_NEXT_LCSSA]]
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; CHECK: out_of_bounds:
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; CHECK-NEXT: ret i32 -1
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;
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entry:
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%capacity = load i32, ptr %capacity_p, !range !0
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%num_elements = load i32, ptr %num_elements_p, !range !0
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %backedge]
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%bytes_to_write = sub i32 %capacity, %iv
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%capacity_check = icmp ule i32 %bytes_to_write, 3
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br i1 %capacity_check, label %out_of_bounds, label %backedge
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backedge:
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%el.ptr = getelementptr i32, ptr %p, i32 %iv
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store i32 1, ptr %el.ptr
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%iv.next = add nuw nsw i32 %iv, 4
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%loop_cond = icmp slt i32 %iv.next, %num_elements
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br i1 %loop_cond, label %loop, label %exit
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exit:
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ret i32 %iv.next
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out_of_bounds:
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ret i32 -1
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}
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!0 = !{i32 1, i32 2147483648}
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