316 lines
16 KiB
LLVM
316 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes='default<O3>' -enable-matrix -S %s | FileCheck %s
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target triple = "arm64-apple-ios"
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define void @matrix_extract_insert_scalar(i32 %i, i32 %k, i32 %j, ptr nonnull align 8 dereferenceable(1800) %A, ptr nonnull align 8 dereferenceable(1800) %B) #0 {
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; CHECK-LABEL: @matrix_extract_insert_scalar(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV:%.*]] = zext i32 [[K:%.*]] to i64
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; CHECK-NEXT: [[CONV1:%.*]] = zext i32 [[J:%.*]] to i64
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; CHECK-NEXT: [[TMP0:%.*]] = mul nuw nsw i64 [[CONV1]], 15
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; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], [[CONV]]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[TMP1]], 225
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP2]])
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <225 x double>, ptr [[A:%.*]], i64 0, i64 [[TMP1]]
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; CHECK-NEXT: [[MATRIXEXT:%.*]] = load double, ptr [[TMP3]], align 8
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; CHECK-NEXT: [[CONV2:%.*]] = zext i32 [[I:%.*]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP0]], [[CONV2]]
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; CHECK-NEXT: [[TMP5:%.*]] = icmp ult i64 [[TMP4]], 225
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP5]])
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds <225 x double>, ptr [[B:%.*]], i64 0, i64 [[TMP4]]
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; CHECK-NEXT: [[MATRIXEXT4:%.*]] = load double, ptr [[TMP6]], align 8
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; CHECK-NEXT: [[MUL:%.*]] = fmul double [[MATRIXEXT]], [[MATRIXEXT4]]
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP1]]
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; CHECK-NEXT: [[MATRIXEXT7:%.*]] = load double, ptr [[TMP7]], align 8
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; CHECK-NEXT: [[SUB:%.*]] = fsub double [[MATRIXEXT7]], [[MUL]]
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; CHECK-NEXT: store double [[SUB]], ptr [[TMP7]], align 8
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; CHECK-NEXT: ret void
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;
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entry:
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%i.addr = alloca i32, align 4
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%k.addr = alloca i32, align 4
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%j.addr = alloca i32, align 4
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%A.addr = alloca ptr, align 8
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%B.addr = alloca ptr, align 8
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store i32 %i, ptr %i.addr, align 4
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store i32 %k, ptr %k.addr, align 4
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store i32 %j, ptr %j.addr, align 4
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store ptr %A, ptr %A.addr, align 8
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store ptr %B, ptr %B.addr, align 8
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%0 = load i32, ptr %k.addr, align 4
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%conv = zext i32 %0 to i64
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%1 = load i32, ptr %j.addr, align 4
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%conv1 = zext i32 %1 to i64
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%2 = mul i64 %conv1, 15
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%3 = add i64 %2, %conv
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%4 = icmp ult i64 %3, 225
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call void @llvm.assume(i1 %4)
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%5 = load ptr, ptr %A.addr, align 8
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%6 = load <225 x double>, ptr %5, align 8
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%matrixext = extractelement <225 x double> %6, i64 %3
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%7 = load i32, ptr %i.addr, align 4
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%conv2 = zext i32 %7 to i64
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%8 = load i32, ptr %j.addr, align 4
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%conv3 = zext i32 %8 to i64
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%9 = mul i64 %conv3, 15
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%10 = add i64 %9, %conv2
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%11 = icmp ult i64 %10, 225
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call void @llvm.assume(i1 %11)
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%12 = load ptr, ptr %B.addr, align 8
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%13 = load <225 x double>, ptr %12, align 8
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%matrixext4 = extractelement <225 x double> %13, i64 %10
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%mul = fmul double %matrixext, %matrixext4
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%14 = load ptr, ptr %B.addr, align 8
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%15 = load i32, ptr %k.addr, align 4
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%conv5 = zext i32 %15 to i64
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%16 = load i32, ptr %j.addr, align 4
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%conv6 = zext i32 %16 to i64
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%17 = mul i64 %conv6, 15
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%18 = add i64 %17, %conv5
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%19 = icmp ult i64 %18, 225
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call void @llvm.assume(i1 %19)
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%20 = load <225 x double>, ptr %14, align 8
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%matrixext7 = extractelement <225 x double> %20, i64 %18
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%sub = fsub double %matrixext7, %mul
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%21 = icmp ult i64 %18, 225
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call void @llvm.assume(i1 %21)
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%22 = load <225 x double>, ptr %14, align 8
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%matins = insertelement <225 x double> %22, double %sub, i64 %18
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store <225 x double> %matins, ptr %14, align 8
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ret void
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}
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define void @matrix_extract_insert_loop(i32 %i, ptr nonnull align 8 dereferenceable(1800) %A, ptr nonnull align 8 dereferenceable(1800) %B) {
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; CHECK-LABEL: @matrix_extract_insert_loop(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP210_NOT:%.*]] = icmp eq i32 [[I:%.*]], 0
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; CHECK-NEXT: [[CONV6:%.*]] = zext i32 [[I]] to i64
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; CHECK-NEXT: br i1 [[CMP210_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER_US:%.*]]
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; CHECK: for.cond1.preheader.us:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[I]], 225
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP0]])
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds <225 x double>, ptr [[B:%.*]], i64 0, i64 [[CONV6]]
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; CHECK-NEXT: br label [[FOR_BODY4_US:%.*]]
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; CHECK: for.body4.us:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_COND1_PREHEADER_US]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY4_US]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i64 [[INDVARS_IV]], 225
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP2]])
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <225 x double>, ptr [[A:%.*]], i64 0, i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[MATRIXEXT_US:%.*]] = load double, ptr [[TMP3]], align 8
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; CHECK-NEXT: [[MATRIXEXT8_US:%.*]] = load double, ptr [[TMP1]], align 8
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; CHECK-NEXT: [[MUL_US:%.*]] = fmul double [[MATRIXEXT_US]], [[MATRIXEXT8_US]]
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[MATRIXEXT11_US:%.*]] = load double, ptr [[TMP4]], align 8
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; CHECK-NEXT: [[SUB_US:%.*]] = fsub double [[MATRIXEXT11_US]], [[MUL_US]]
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; CHECK-NEXT: store double [[SUB_US]], ptr [[TMP4]], align 8
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[CONV6]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US:%.*]], label [[FOR_BODY4_US]]
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; CHECK: for.cond1.for.cond.cleanup3_crit_edge.us:
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; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw i64 [[CONV6]], 15
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; CHECK-NEXT: [[TMP6:%.*]] = icmp ult i32 [[I]], 210
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP6]])
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP5]]
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; CHECK-NEXT: br label [[FOR_BODY4_US_1:%.*]]
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; CHECK: for.body4.us.1:
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; CHECK-NEXT: [[INDVARS_IV_1:%.*]] = phi i64 [ 0, [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[FOR_BODY4_US_1]] ]
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; CHECK-NEXT: [[TMP8:%.*]] = add nuw nsw i64 [[INDVARS_IV_1]], 15
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; CHECK-NEXT: [[TMP9:%.*]] = icmp ult i64 [[INDVARS_IV_1]], 210
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP9]])
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds <225 x double>, ptr [[A]], i64 0, i64 [[TMP8]]
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; CHECK-NEXT: [[MATRIXEXT_US_1:%.*]] = load double, ptr [[TMP10]], align 8
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; CHECK-NEXT: [[MATRIXEXT8_US_1:%.*]] = load double, ptr [[TMP7]], align 8
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; CHECK-NEXT: [[MUL_US_1:%.*]] = fmul double [[MATRIXEXT_US_1]], [[MATRIXEXT8_US_1]]
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; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP8]]
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; CHECK-NEXT: [[MATRIXEXT11_US_1:%.*]] = load double, ptr [[TMP11]], align 8
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; CHECK-NEXT: [[SUB_US_1:%.*]] = fsub double [[MATRIXEXT11_US_1]], [[MUL_US_1]]
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; CHECK-NEXT: store double [[SUB_US_1]], ptr [[TMP11]], align 8
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; CHECK-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV_1]], 1
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; CHECK-NEXT: [[EXITCOND_NOT_1:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_1]], [[CONV6]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT_1]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US_1:%.*]], label [[FOR_BODY4_US_1]]
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; CHECK: for.cond1.for.cond.cleanup3_crit_edge.us.1:
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; CHECK-NEXT: [[TMP12:%.*]] = add nuw nsw i64 [[CONV6]], 30
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; CHECK-NEXT: [[TMP13:%.*]] = icmp ult i32 [[I]], 195
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP13]])
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP12]]
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; CHECK-NEXT: br label [[FOR_BODY4_US_2:%.*]]
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; CHECK: for.body4.us.2:
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; CHECK-NEXT: [[INDVARS_IV_2:%.*]] = phi i64 [ 0, [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US_1]] ], [ [[INDVARS_IV_NEXT_2:%.*]], [[FOR_BODY4_US_2]] ]
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; CHECK-NEXT: [[TMP15:%.*]] = add nuw nsw i64 [[INDVARS_IV_2]], 30
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; CHECK-NEXT: [[TMP16:%.*]] = icmp ult i64 [[INDVARS_IV_2]], 195
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP16]])
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; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds <225 x double>, ptr [[A]], i64 0, i64 [[TMP15]]
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; CHECK-NEXT: [[MATRIXEXT_US_2:%.*]] = load double, ptr [[TMP17]], align 8
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; CHECK-NEXT: [[MATRIXEXT8_US_2:%.*]] = load double, ptr [[TMP14]], align 8
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; CHECK-NEXT: [[MUL_US_2:%.*]] = fmul double [[MATRIXEXT_US_2]], [[MATRIXEXT8_US_2]]
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; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP15]]
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; CHECK-NEXT: [[MATRIXEXT11_US_2:%.*]] = load double, ptr [[TMP18]], align 8
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; CHECK-NEXT: [[SUB_US_2:%.*]] = fsub double [[MATRIXEXT11_US_2]], [[MUL_US_2]]
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; CHECK-NEXT: store double [[SUB_US_2]], ptr [[TMP18]], align 8
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; CHECK-NEXT: [[INDVARS_IV_NEXT_2]] = add nuw nsw i64 [[INDVARS_IV_2]], 1
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; CHECK-NEXT: [[EXITCOND_NOT_2:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_2]], [[CONV6]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT_2]], label [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US_2:%.*]], label [[FOR_BODY4_US_2]]
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; CHECK: for.cond1.for.cond.cleanup3_crit_edge.us.2:
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; CHECK-NEXT: [[TMP19:%.*]] = add nuw nsw i64 [[CONV6]], 45
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; CHECK-NEXT: [[TMP20:%.*]] = icmp ult i32 [[I]], 180
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP20]])
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; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP19]]
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; CHECK-NEXT: br label [[FOR_BODY4_US_3:%.*]]
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; CHECK: for.body4.us.3:
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; CHECK-NEXT: [[INDVARS_IV_3:%.*]] = phi i64 [ 0, [[FOR_COND1_FOR_COND_CLEANUP3_CRIT_EDGE_US_2]] ], [ [[INDVARS_IV_NEXT_3:%.*]], [[FOR_BODY4_US_3]] ]
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; CHECK-NEXT: [[TMP22:%.*]] = add nuw nsw i64 [[INDVARS_IV_3]], 45
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; CHECK-NEXT: [[TMP23:%.*]] = icmp ult i64 [[INDVARS_IV_3]], 180
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP23]])
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; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds <225 x double>, ptr [[A]], i64 0, i64 [[TMP22]]
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; CHECK-NEXT: [[MATRIXEXT_US_3:%.*]] = load double, ptr [[TMP24]], align 8
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; CHECK-NEXT: [[MATRIXEXT8_US_3:%.*]] = load double, ptr [[TMP21]], align 8
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; CHECK-NEXT: [[MUL_US_3:%.*]] = fmul double [[MATRIXEXT_US_3]], [[MATRIXEXT8_US_3]]
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; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds <225 x double>, ptr [[B]], i64 0, i64 [[TMP22]]
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; CHECK-NEXT: [[MATRIXEXT11_US_3:%.*]] = load double, ptr [[TMP25]], align 8
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; CHECK-NEXT: [[SUB_US_3:%.*]] = fsub double [[MATRIXEXT11_US_3]], [[MUL_US_3]]
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; CHECK-NEXT: store double [[SUB_US_3]], ptr [[TMP25]], align 8
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; CHECK-NEXT: [[INDVARS_IV_NEXT_3]] = add nuw nsw i64 [[INDVARS_IV_3]], 1
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; CHECK-NEXT: [[EXITCOND_NOT_3:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_3]], [[CONV6]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT_3]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY4_US_3]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: ret void
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;
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entry:
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%i.addr = alloca i32, align 4
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%A.addr = alloca ptr, align 8
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%B.addr = alloca ptr, align 8
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%j = alloca i32, align 4
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%cleanup.dest.slot = alloca i32, align 4
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%k = alloca i32, align 4
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store i32 %i, ptr %i.addr, align 4
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store ptr %A, ptr %A.addr, align 8
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store ptr %B, ptr %B.addr, align 8
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call void @llvm.lifetime.start.p0(i64 4, ptr %j) #3
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store i32 0, ptr %j, align 4
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br label %for.cond
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for.cond: ; preds = %for.inc12, %entry
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%0 = load i32, ptr %j, align 4
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%cmp = icmp ult i32 %0, 4
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond
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store i32 2, ptr %cleanup.dest.slot, align 4
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call void @llvm.lifetime.end.p0(i64 4, ptr %j) #3
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br label %for.end14
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for.body: ; preds = %for.cond
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call void @llvm.lifetime.start.p0(i64 4, ptr %k) #3
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store i32 0, ptr %k, align 4
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br label %for.cond1
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for.cond1: ; preds = %for.inc, %for.body
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%1 = load i32, ptr %k, align 4
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%2 = load i32, ptr %i.addr, align 4
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%cmp2 = icmp ult i32 %1, %2
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br i1 %cmp2, label %for.body4, label %for.cond.cleanup3
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for.cond.cleanup3: ; preds = %for.cond1
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store i32 5, ptr %cleanup.dest.slot, align 4
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call void @llvm.lifetime.end.p0(i64 4, ptr %k) #3
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br label %for.end
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for.body4: ; preds = %for.cond1
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%3 = load i32, ptr %k, align 4
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%conv = zext i32 %3 to i64
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%4 = load i32, ptr %j, align 4
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%conv5 = zext i32 %4 to i64
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%5 = mul i64 %conv5, 15
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%6 = add i64 %5, %conv
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%7 = icmp ult i64 %6, 225
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call void @llvm.assume(i1 %7)
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%8 = load ptr, ptr %A.addr, align 8
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%9 = load <225 x double>, ptr %8, align 8
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%matrixext = extractelement <225 x double> %9, i64 %6
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%10 = load i32, ptr %i.addr, align 4
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%conv6 = zext i32 %10 to i64
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%11 = load i32, ptr %j, align 4
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%conv7 = zext i32 %11 to i64
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%12 = mul i64 %conv7, 15
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%13 = add i64 %12, %conv6
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%14 = icmp ult i64 %13, 225
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call void @llvm.assume(i1 %14)
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%15 = load ptr, ptr %B.addr, align 8
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%16 = load <225 x double>, ptr %15, align 8
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%matrixext8 = extractelement <225 x double> %16, i64 %13
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%mul = fmul double %matrixext, %matrixext8
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%17 = load ptr, ptr %B.addr, align 8
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%18 = load i32, ptr %k, align 4
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%conv9 = zext i32 %18 to i64
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%19 = load i32, ptr %j, align 4
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%conv10 = zext i32 %19 to i64
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%20 = mul i64 %conv10, 15
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%21 = add i64 %20, %conv9
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%22 = icmp ult i64 %21, 225
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call void @llvm.assume(i1 %22)
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%23 = load <225 x double>, ptr %17, align 8
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%matrixext11 = extractelement <225 x double> %23, i64 %21
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%sub = fsub double %matrixext11, %mul
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%24 = icmp ult i64 %21, 225
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call void @llvm.assume(i1 %24)
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%25 = load <225 x double>, ptr %17, align 8
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%matins = insertelement <225 x double> %25, double %sub, i64 %21
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store <225 x double> %matins, ptr %17, align 8
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br label %for.inc
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for.inc: ; preds = %for.body4
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%26 = load i32, ptr %k, align 4
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%inc = add i32 %26, 1
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store i32 %inc, ptr %k, align 4
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br label %for.cond1
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for.end: ; preds = %for.cond.cleanup3
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br label %for.inc12
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for.inc12: ; preds = %for.end
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%27 = load i32, ptr %j, align 4
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%inc13 = add i32 %27, 1
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store i32 %inc13, ptr %j, align 4
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br label %for.cond
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for.end14: ; preds = %for.cond.cleanup
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ret void
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}
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; Function Attrs: argmemonly nofree nosync nounwind willreturn
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declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1
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; Function Attrs: inaccessiblememonly nofree nosync nounwind willreturn
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declare void @llvm.assume(i1 noundef) #2
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; Function Attrs: argmemonly nofree nosync nounwind willreturn
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declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1
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; Function Attrs: nounwind ssp uwtable mustprogress
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define <4 x float> @reverse_hadd_v4f32(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: @reverse_hadd_v4f32(
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[B:%.*]], <4 x float> [[A:%.*]], <4 x i32> <i32 2, i32 0, i32 6, i32 4>
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; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[B]], <4 x float> [[A]], <4 x i32> <i32 3, i32 1, i32 7, i32 5>
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; CHECK-NEXT: [[TMP3:%.*]] = fadd <4 x float> [[TMP1]], [[TMP2]]
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; CHECK-NEXT: ret <4 x float> [[TMP3]]
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;
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%vecext = extractelement <4 x float> %a, i32 0
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%vecext1 = extractelement <4 x float> %a, i32 1
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%add = fadd float %vecext, %vecext1
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%vecinit = insertelement <4 x float> undef, float %add, i32 0
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%vecext2 = extractelement <4 x float> %a, i32 2
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%vecext3 = extractelement <4 x float> %a, i32 3
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%add4 = fadd float %vecext2, %vecext3
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%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 1
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%vecext6 = extractelement <4 x float> %b, i32 0
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%vecext7 = extractelement <4 x float> %b, i32 1
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%add8 = fadd float %vecext6, %vecext7
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%vecinit9 = insertelement <4 x float> %vecinit5, float %add8, i32 2
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%vecext10 = extractelement <4 x float> %b, i32 2
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%vecext11 = extractelement <4 x float> %b, i32 3
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%add12 = fadd float %vecext10, %vecext11
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%vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 3
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%shuffle = shufflevector <4 x float> %vecinit13, <4 x float> %a, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x float> %shuffle
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}
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