193 lines
14 KiB
LLVM
193 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -mtriple=amdgcn-- -S -passes=separate-const-offset-from-gep,gvn -reassociate-geps-verify-no-dead-code < %s | FileCheck -check-prefix=IR %s
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target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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@array = internal addrspace(4) constant [4096 x [32 x float]] zeroinitializer, align 4
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define amdgpu_kernel void @sum_of_array(i32 %x, i32 %y, ptr addrspace(1) nocapture %output) {
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; IR-LABEL: define amdgpu_kernel void @sum_of_array(
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; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr addrspace(1) nocapture [[OUTPUT:%.*]]) {
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; IR-NEXT: [[TMP:%.*]] = sext i32 [[Y]] to i64
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; IR-NEXT: [[TMP1:%.*]] = sext i32 [[X]] to i64
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; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 [[TMP1]], i64 [[TMP]]
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; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 4
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; IR-NEXT: [[TMP144:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 128
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; IR-NEXT: [[TMP187:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 132
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; IR-NEXT: store float 0.000000e+00, ptr addrspace(1) [[OUTPUT]], align 4
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; IR-NEXT: ret void
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;
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%tmp = sext i32 %y to i64
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%tmp1 = sext i32 %x to i64
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%tmp2 = getelementptr inbounds [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 %tmp1, i64 %tmp
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%tmp4 = load float, ptr addrspace(4) %tmp2, align 4
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%tmp5 = fadd float %tmp4, 0.000000e+00
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%tmp6 = add i32 %y, 1
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%tmp7 = sext i32 %tmp6 to i64
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%tmp8 = getelementptr inbounds [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 %tmp1, i64 %tmp7
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%tmp10 = load float, ptr addrspace(4) %tmp8, align 4
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%tmp11 = fadd float %tmp5, %tmp10
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%tmp12 = add i32 %x, 1
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%tmp13 = sext i32 %tmp12 to i64
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%tmp14 = getelementptr inbounds [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 %tmp13, i64 %tmp
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%tmp16 = load float, ptr addrspace(4) %tmp14, align 4
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%tmp17 = fadd float %tmp11, %tmp16
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%tmp18 = getelementptr inbounds [4096 x [32 x float]], ptr addrspace(4) @array, i64 0, i64 %tmp13, i64 %tmp7
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%tmp20 = load float, ptr addrspace(4) %tmp18, align 4
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%tmp21 = fadd float %tmp17, %tmp20
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store float %tmp21, ptr addrspace(1) %output, align 4
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ret void
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}
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@array2 = internal addrspace(4) constant [4096 x [4 x float]] zeroinitializer, align 4
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; Some of the indices go over the maximum mubuf offset, so don't split them.
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define amdgpu_kernel void @sum_of_array_over_max_mubuf_offset(i32 %x, i32 %y, ptr addrspace(1) nocapture %output) {
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; IR-LABEL: define amdgpu_kernel void @sum_of_array_over_max_mubuf_offset(
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; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr addrspace(1) nocapture [[OUTPUT:%.*]]) {
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; IR-NEXT: [[TMP:%.*]] = sext i32 [[Y]] to i64
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; IR-NEXT: [[TMP1:%.*]] = sext i32 [[X]] to i64
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; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP1]], i64 [[TMP]]
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; IR-NEXT: [[TMP6:%.*]] = add i32 [[Y]], 255
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; IR-NEXT: [[TMP7:%.*]] = sext i32 [[TMP6]] to i64
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; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[TMP2]], i64 1020
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; IR-NEXT: [[TMP12:%.*]] = add i32 [[X]], 256
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; IR-NEXT: [[TMP13:%.*]] = sext i32 [[TMP12]] to i64
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; IR-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP13]], i64 [[TMP]]
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; IR-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 [[TMP13]], i64 [[TMP7]]
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; IR-NEXT: store float 0.000000e+00, ptr addrspace(1) [[OUTPUT]], align 4
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; IR-NEXT: ret void
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;
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%tmp = sext i32 %y to i64
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%tmp1 = sext i32 %x to i64
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%tmp2 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %tmp1, i64 %tmp
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%tmp4 = load float, ptr addrspace(4) %tmp2, align 4
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%tmp5 = fadd float %tmp4, 0.000000e+00
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%tmp6 = add i32 %y, 255
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%tmp7 = sext i32 %tmp6 to i64
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%tmp8 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %tmp1, i64 %tmp7
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%tmp10 = load float, ptr addrspace(4) %tmp8, align 4
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%tmp11 = fadd float %tmp5, %tmp10
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%tmp12 = add i32 %x, 256
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%tmp13 = sext i32 %tmp12 to i64
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%tmp14 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %tmp13, i64 %tmp
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%tmp16 = load float, ptr addrspace(4) %tmp14, align 4
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%tmp17 = fadd float %tmp11, %tmp16
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%tmp18 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(4) @array2, i64 0, i64 %tmp13, i64 %tmp7
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%tmp20 = load float, ptr addrspace(4) %tmp18, align 4
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%tmp21 = fadd float %tmp17, %tmp20
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store float %tmp21, ptr addrspace(1) %output, align 4
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ret void
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}
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@lds_array = internal addrspace(3) global [4096 x [4 x float]] undef, align 4
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; DS instructions have a larger immediate offset, so make sure these are OK.
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define amdgpu_kernel void @sum_of_lds_array_over_max_mubuf_offset(i32 %x, i32 %y, ptr addrspace(1) nocapture %output) {
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; IR-LABEL: define amdgpu_kernel void @sum_of_lds_array_over_max_mubuf_offset(
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; IR-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], ptr addrspace(1) nocapture [[OUTPUT:%.*]]) {
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; IR-NEXT: [[TMP2:%.*]] = getelementptr [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 [[X]], i32 [[Y]]
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; IR-NEXT: [[TMP4:%.*]] = load float, ptr addrspace(3) [[TMP2]], align 4
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; IR-NEXT: [[TMP5:%.*]] = fadd float [[TMP4]], 0.000000e+00
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; IR-NEXT: [[TMP82:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i32 1020
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; IR-NEXT: [[TMP10:%.*]] = load float, ptr addrspace(3) [[TMP82]], align 4
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; IR-NEXT: [[TMP11:%.*]] = fadd float [[TMP5]], [[TMP10]]
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; IR-NEXT: [[TMP144:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i32 64512
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; IR-NEXT: [[TMP16:%.*]] = load float, ptr addrspace(3) [[TMP144]], align 4
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; IR-NEXT: [[TMP17:%.*]] = fadd float [[TMP11]], [[TMP16]]
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; IR-NEXT: [[TMP187:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP2]], i32 65532
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; IR-NEXT: [[TMP20:%.*]] = load float, ptr addrspace(3) [[TMP187]], align 4
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; IR-NEXT: [[TMP21:%.*]] = fadd float [[TMP17]], [[TMP20]]
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; IR-NEXT: store float [[TMP21]], ptr addrspace(1) [[OUTPUT]], align 4
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; IR-NEXT: ret void
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;
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%tmp2 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 %x, i32 %y
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%tmp4 = load float, ptr addrspace(3) %tmp2, align 4
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%tmp5 = fadd float %tmp4, 0.000000e+00
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%tmp6 = add i32 %y, 255
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%tmp8 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 %x, i32 %tmp6
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%tmp10 = load float, ptr addrspace(3) %tmp8, align 4
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%tmp11 = fadd float %tmp5, %tmp10
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%tmp12 = add i32 %x, 4032
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%tmp14 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 %tmp12, i32 %y
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%tmp16 = load float, ptr addrspace(3) %tmp14, align 4
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%tmp17 = fadd float %tmp11, %tmp16
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%tmp18 = getelementptr inbounds [4096 x [4 x float]], ptr addrspace(3) @lds_array, i32 0, i32 %tmp12, i32 %tmp6
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%tmp20 = load float, ptr addrspace(3) %tmp18, align 4
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%tmp21 = fadd float %tmp17, %tmp20
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store float %tmp21, ptr addrspace(1) %output, align 4
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ret void
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}
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define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @keep_metadata(ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #5 {
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; IR-LABEL: define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @keep_metadata(
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; IR-SAME: ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP0:%.*]], ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP1:%.*]], ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP2:%.*]], ptr addrspace(4) inreg noalias dereferenceable(18446744073709551615) [[TMP3:%.*]], float inreg [[TMP4:%.*]], i32 inreg [[TMP5:%.*]], <2 x i32> [[TMP6:%.*]], <2 x i32> [[TMP7:%.*]], <2 x i32> [[TMP8:%.*]], <3 x i32> [[TMP9:%.*]], <2 x i32> [[TMP10:%.*]], <2 x i32> [[TMP11:%.*]], <2 x i32> [[TMP12:%.*]], float [[TMP13:%.*]], float [[TMP14:%.*]], float [[TMP15:%.*]], float [[TMP16:%.*]], float [[TMP17:%.*]], i32 [[TMP18:%.*]], i32 [[TMP19:%.*]], float [[TMP20:%.*]], i32 [[TMP21:%.*]]) #[[ATTR0:[0-9]+]] {
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; IR-NEXT: main_body:
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; IR-NEXT: [[TMP22:%.*]] = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 [[TMP5]]) #[[ATTR3:[0-9]+]]
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; IR-NEXT: [[TMP23:%.*]] = bitcast float [[TMP22]] to i32
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; IR-NEXT: [[TMP24:%.*]] = shl i32 [[TMP23]], 1
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; IR-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP24]] to i64
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; IR-NEXT: [[TMP25:%.*]] = getelementptr [0 x <8 x i32>], ptr addrspace(4) [[TMP1]], i64 0, i64 [[IDXPROM1]], !amdgpu.uniform [[META0:![0-9]+]]
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; IR-NEXT: [[TMP26:%.*]] = load <8 x i32>, ptr addrspace(4) [[TMP25]], align 32, !invariant.load [[META0]]
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; IR-NEXT: [[TMP27:%.*]] = shl i32 [[TMP23]], 2
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; IR-NEXT: [[TMP28:%.*]] = sext i32 [[TMP27]] to i64
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; IR-NEXT: [[TMP29:%.*]] = getelementptr [0 x <4 x i32>], ptr addrspace(4) [[TMP1]], i64 0, i64 [[TMP28]], !amdgpu.uniform [[META0]]
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; IR-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr addrspace(4) [[TMP29]], i64 48, !amdgpu.uniform [[META0]]
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; IR-NEXT: [[TMP31:%.*]] = load <4 x i32>, ptr addrspace(4) [[TMP30]], align 16, !invariant.load [[META0]]
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; IR-NEXT: [[TMP32:%.*]] = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> zeroinitializer, <8 x i32> [[TMP26]], <4 x i32> [[TMP31]], i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #[[ATTR3]]
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; IR-NEXT: [[TMP33:%.*]] = extractelement <4 x float> [[TMP32]], i32 0
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; IR-NEXT: [[TMP34:%.*]] = extractelement <4 x float> [[TMP32]], i32 1
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; IR-NEXT: [[TMP35:%.*]] = extractelement <4 x float> [[TMP32]], i32 2
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; IR-NEXT: [[TMP36:%.*]] = extractelement <4 x float> [[TMP32]], i32 3
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; IR-NEXT: [[TMP37:%.*]] = bitcast float [[TMP4]] to i32
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; IR-NEXT: [[TMP38:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 [[TMP37]], 4
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; IR-NEXT: [[TMP39:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP38]], float [[TMP33]], 5
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; IR-NEXT: [[TMP40:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP39]], float [[TMP34]], 6
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; IR-NEXT: [[TMP41:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP40]], float [[TMP35]], 7
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; IR-NEXT: [[TMP42:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP41]], float [[TMP36]], 8
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; IR-NEXT: [[TMP43:%.*]] = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP42]], float [[TMP20]], 19
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; IR-NEXT: ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> [[TMP43]]
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;
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main_body:
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%22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %5) #8
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%23 = bitcast float %22 to i32
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%24 = shl i32 %23, 1
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%25 = getelementptr [0 x <8 x i32>], ptr addrspace(4) %1, i32 0, i32 %24, !amdgpu.uniform !0
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%26 = load <8 x i32>, ptr addrspace(4) %25, align 32, !invariant.load !0
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%27 = shl i32 %23, 2
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%28 = or i32 %27, 3
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%29 = getelementptr [0 x <4 x i32>], ptr addrspace(4) %1, i32 0, i32 %28, !amdgpu.uniform !0
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%30 = load <4 x i32>, ptr addrspace(4) %29, align 16, !invariant.load !0
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%31 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> zeroinitializer, <8 x i32> %26, <4 x i32> %30, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #8
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%32 = extractelement <4 x float> %31, i32 0
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%33 = extractelement <4 x float> %31, i32 1
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%34 = extractelement <4 x float> %31, i32 2
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%35 = extractelement <4 x float> %31, i32 3
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%36 = bitcast float %4 to i32
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%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %36, 4
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%38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %37, float %32, 5
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%39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 6
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%40 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 7
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%41 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %40, float %35, 8
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%42 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %41, float %20, 19
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ret <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %42
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}
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; Function Attrs: nounwind readnone speculatable
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declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #6
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; Function Attrs: nounwind readonly
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declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #7
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!0 = !{}
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attributes #5 = { "InitialPSInputAddr"="45175" }
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attributes #6 = { nounwind readnone speculatable }
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attributes #7 = { nounwind readonly }
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attributes #8 = { nounwind readnone }
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;.
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; IR: [[META0]] = !{}
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;.
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