156 lines
4.6 KiB
LLVM
156 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S -hoist-common-insts=true | FileCheck %s
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declare void @bar(i32)
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define void @test(i1 %P, ptr %Q) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: common.ret:
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; CHECK-NEXT: store i32 1, ptr [[Q:%.*]], align 4
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; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[Q]], align 4
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; CHECK-NEXT: call void @bar(i32 [[A]])
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; CHECK-NEXT: ret void
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;
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br i1 %P, label %T, label %F
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T: ; preds = %0
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store i32 1, ptr %Q
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%A = load i32, ptr %Q ; <i32> [#uses=1]
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call void @bar( i32 %A )
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ret void
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F: ; preds = %0
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store i32 1, ptr %Q
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%B = load i32, ptr %Q ; <i32> [#uses=1]
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call void @bar( i32 %B )
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ret void
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}
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define void @test_switch(i64 %i, ptr %Q) {
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; CHECK-LABEL: @test_switch(
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; CHECK-NEXT: common.ret:
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; CHECK-NEXT: store i32 1, ptr [[Q:%.*]], align 4
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; CHECK-NEXT: [[A:%.*]] = load i32, ptr [[Q]], align 4
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; CHECK-NEXT: call void @bar(i32 [[A]])
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; CHECK-NEXT: ret void
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;
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switch i64 %i, label %bb0 [
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i64 1, label %bb1
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i64 2, label %bb2
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]
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bb0: ; preds = %0
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store i32 1, ptr %Q
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%A = load i32, ptr %Q ; <i32> [#uses=1]
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call void @bar( i32 %A )
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ret void
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bb1: ; preds = %0
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store i32 1, ptr %Q
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%B = load i32, ptr %Q ; <i32> [#uses=1]
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call void @bar( i32 %B )
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ret void
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bb2: ; preds = %0
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store i32 1, ptr %Q
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%C = load i32, ptr %Q ; <i32> [#uses=1]
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call void @bar( i32 %C )
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ret void
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}
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; We ensure that we examine all instructions during each iteration to confirm the presence of a terminating one.
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define void @test_switch_reach_terminator(i64 %i, ptr %p) {
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; CHECK-LABEL: @test_switch_reach_terminator(
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; CHECK-NEXT: switch i64 [[I:%.*]], label [[BB0:%.*]] [
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; CHECK-NEXT: i64 1, label [[BB1:%.*]]
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; CHECK-NEXT: i64 2, label [[COMMON_RET:%.*]]
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; CHECK-NEXT: ]
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; CHECK: common.ret:
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; CHECK-NEXT: ret void
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; CHECK: bb0:
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; CHECK-NEXT: store i32 1, ptr [[P:%.*]], align 4
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; CHECK-NEXT: br label [[COMMON_RET]]
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; CHECK: bb1:
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; CHECK-NEXT: store i32 2, ptr [[P]], align 4
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; CHECK-NEXT: br label [[COMMON_RET]]
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;
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switch i64 %i, label %bb0 [
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i64 1, label %bb1
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i64 2, label %bb2
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]
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bb0: ; preds = %0
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store i32 1, ptr %p
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ret void
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bb1: ; preds = %0
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store i32 2, ptr %p
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ret void
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bb2: ; preds = %0
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ret void
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}
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define i1 @common_instr_on_switch(i64 %a, i64 %b, i64 %c) unnamed_addr {
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; CHECK-LABEL: @common_instr_on_switch(
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; CHECK-NEXT: start:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[B:%.*]], [[C:%.*]]
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; CHECK-NEXT: ret i1 [[TMP0]]
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;
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start:
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switch i64 %a, label %bb0 [
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i64 1, label %bb1
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i64 2, label %bb2
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]
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bb0: ; preds = %start
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%0 = icmp eq i64 %b, %c
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br label %exit
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bb1: ; preds = %start
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%1 = icmp eq i64 %b, %c
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br label %exit
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bb2: ; preds = %start
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%2 = icmp eq i64 %b, %c
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br label %exit
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exit: ; preds = %bb2, %bb1, %bb0
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%result = phi i1 [ %0, %bb0 ], [ %1, %bb1 ], [ %2, %bb2 ]
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ret i1 %result
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}
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define i1 @partial_common_instr_on_switch(i64 %a, i64 %b, i64 %c) unnamed_addr {
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; CHECK-LABEL: @partial_common_instr_on_switch(
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; CHECK-NEXT: start:
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; CHECK-NEXT: switch i64 [[A:%.*]], label [[BB0:%.*]] [
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; CHECK-NEXT: i64 1, label [[BB1:%.*]]
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; CHECK-NEXT: i64 2, label [[BB2:%.*]]
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; CHECK-NEXT: ]
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; CHECK: bb0:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i64 [[B:%.*]], [[C:%.*]]
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; CHECK-NEXT: br label [[EXIT:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[B]], [[C]]
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: bb2:
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[B]], [[C]]
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: [[RESULT:%.*]] = phi i1 [ [[TMP0]], [[BB0]] ], [ [[TMP1]], [[BB1]] ], [ [[TMP2]], [[BB2]] ]
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; CHECK-NEXT: ret i1 [[RESULT]]
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;
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start:
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switch i64 %a, label %bb0 [
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i64 1, label %bb1
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i64 2, label %bb2
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]
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bb0: ; preds = %start
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%0 = icmp eq i64 %b, %c
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br label %exit
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bb1: ; preds = %start
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%1 = icmp ne i64 %b, %c
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br label %exit
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bb2: ; preds = %start
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%2 = icmp eq i64 %b, %c
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br label %exit
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exit: ; preds = %bb2, %bb1, %bb0
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%result = phi i1 [ %0, %bb0 ], [ %1, %bb1 ], [ %2, %bb2 ]
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ret i1 %result
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}
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