238 lines
8.4 KiB
C++
238 lines
8.4 KiB
C++
//==- utils/TableGen/X86CompressEVEXTablesEmitter.cpp - X86 backend-*- C++ -*-//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This tablegen backend is responsible for emitting the X86 backend EVEX
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/// compression tables.
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///
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//===----------------------------------------------------------------------===//
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#include "CodeGenInstruction.h"
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#include "CodeGenTarget.h"
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#include "X86RecognizableInstr.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <map>
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#include <set>
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using namespace llvm;
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using namespace X86Disassembler;
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namespace {
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const std::map<StringRef, StringRef> ManualMap = {
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#define ENTRY(OLD, NEW) {#OLD, #NEW},
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#include "X86ManualCompressEVEXTables.def"
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};
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const std::set<StringRef> NoCompressSet = {
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#define NOCOMP(INSN) #INSN,
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#include "X86ManualCompressEVEXTables.def"
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};
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class X86CompressEVEXTablesEmitter {
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RecordKeeper &Records;
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CodeGenTarget Target;
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// Hold all pontentially compressible EVEX instructions
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std::vector<const CodeGenInstruction *> PreCompressionInsts;
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// Hold all compressed instructions. Divided into groups with same opcodes
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// to make the search more efficient
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std::map<uint64_t, std::vector<const CodeGenInstruction *>> CompressedInsts;
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typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *>
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Entry;
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typedef std::map<const Record *, std::vector<const CodeGenInstruction *>>
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PredicateInstMap;
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std::vector<Entry> Table;
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// Hold all compressed instructions that need to check predicate
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PredicateInstMap PredicateInsts;
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public:
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X86CompressEVEXTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
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// run - Output X86 EVEX compression tables.
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void run(raw_ostream &OS);
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private:
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// Prints the given table as a C++ array of type X86CompressEVEXTableEntry
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void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
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// Prints function which checks target feature for compressed instructions.
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void printCheckPredicate(const PredicateInstMap &PredicateInsts,
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raw_ostream &OS);
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};
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void X86CompressEVEXTablesEmitter::printTable(const std::vector<Entry> &Table,
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raw_ostream &OS) {
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OS << "static const X86CompressEVEXTableEntry X86CompressEVEXTable[] = {\n";
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// Print all entries added to the table
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for (const auto &Pair : Table)
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OS << " { X86::" << Pair.first->TheDef->getName()
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<< ", X86::" << Pair.second->TheDef->getName() << " },\n";
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OS << "};\n\n";
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}
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void X86CompressEVEXTablesEmitter::printCheckPredicate(
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const PredicateInstMap &PredicateInsts, raw_ostream &OS) {
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OS << "static bool checkPredicate(unsigned Opc, const X86Subtarget *Subtarget) {\n"
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<< " switch (Opc) {\n"
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<< " default: return true;\n";
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for (const auto &[Key, Val] : PredicateInsts) {
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for (const auto &Inst : Val)
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OS << " case X86::" << Inst->TheDef->getName() << ":\n";
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OS << " return " << Key->getValueAsString("CondString") << ";\n";
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}
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OS << " }\n";
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OS << "}\n\n";
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}
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static uint8_t byteFromBitsInit(const BitsInit *B) {
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unsigned N = B->getNumBits();
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assert(N <= 8 && "Field is too large for uint8_t!");
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uint8_t Value = 0;
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for (unsigned I = 0; I != N; ++I) {
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BitInit *Bit = cast<BitInit>(B->getBit(I));
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Value |= Bit->getValue() << I;
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}
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return Value;
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}
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class IsMatch {
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const CodeGenInstruction *OldInst;
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public:
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IsMatch(const CodeGenInstruction *OldInst) : OldInst(OldInst) {}
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bool operator()(const CodeGenInstruction *NewInst) {
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RecognizableInstrBase NewRI(*NewInst);
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RecognizableInstrBase OldRI(*OldInst);
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// Return false if any of the following fields of does not match.
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if (std::make_tuple(OldRI.IsCodeGenOnly, OldRI.OpMap, NewRI.OpPrefix,
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OldRI.HasVEX_4V, OldRI.HasVEX_L, OldRI.HasREX_W,
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OldRI.Form) !=
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std::make_tuple(NewRI.IsCodeGenOnly, NewRI.OpMap, OldRI.OpPrefix,
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NewRI.HasVEX_4V, NewRI.HasVEX_L, NewRI.HasREX_W,
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NewRI.Form))
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return false;
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for (unsigned I = 0, E = OldInst->Operands.size(); I < E; ++I) {
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Record *OldOpRec = OldInst->Operands[I].Rec;
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Record *NewOpRec = NewInst->Operands[I].Rec;
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if (OldOpRec == NewOpRec)
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continue;
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if (isRegisterOperand(OldOpRec) && isRegisterOperand(NewOpRec)) {
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if (getRegOperandSize(OldOpRec) != getRegOperandSize(NewOpRec))
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return false;
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} else if (isMemoryOperand(OldOpRec) && isMemoryOperand(NewOpRec)) {
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if (getMemOperandSize(OldOpRec) != getMemOperandSize(NewOpRec))
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return false;
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} else if (isImmediateOperand(OldOpRec) && isImmediateOperand(NewOpRec)) {
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if (OldOpRec->getValueAsDef("Type") != NewOpRec->getValueAsDef("Type"))
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return false;
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}
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}
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return true;
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}
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};
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void X86CompressEVEXTablesEmitter::run(raw_ostream &OS) {
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emitSourceFileHeader("X86 EVEX compression tables", OS);
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ArrayRef<const CodeGenInstruction *> NumberedInstructions =
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Target.getInstructionsByEnumValue();
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for (const CodeGenInstruction *Inst : NumberedInstructions) {
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const Record *Rec = Inst->TheDef;
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StringRef Name = Rec->getName();
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// _REV instruction should not appear before encoding optimization
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if (!Rec->isSubClassOf("X86Inst") ||
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Rec->getValueAsBit("isAsmParserOnly") || Name.ends_with("_REV"))
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continue;
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// Promoted legacy instruction is in EVEX space, and has REX2-encoding
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// alternative. It's added due to HW design and never emitted by compiler.
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if (byteFromBitsInit(Rec->getValueAsBitsInit("OpMapBits")) ==
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X86Local::T_MAP4 &&
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byteFromBitsInit(Rec->getValueAsBitsInit("explicitOpPrefixBits")) ==
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X86Local::ExplicitEVEX)
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continue;
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if (NoCompressSet.find(Name) != NoCompressSet.end())
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continue;
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RecognizableInstrBase RI(*Inst);
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bool IsND = RI.OpMap == X86Local::T_MAP4 && RI.HasEVEX_B && RI.HasVEX_4V;
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// Add VEX encoded instructions to one of CompressedInsts vectors according
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// to it's opcode.
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if (RI.Encoding == X86Local::VEX)
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CompressedInsts[RI.Opcode].push_back(Inst);
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// Add relevant EVEX encoded instructions to PreCompressionInsts
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else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_L2 &&
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(!RI.HasEVEX_B || IsND))
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PreCompressionInsts.push_back(Inst);
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}
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for (const CodeGenInstruction *Inst : PreCompressionInsts) {
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const Record *Rec = Inst->TheDef;
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uint8_t Opcode = byteFromBitsInit(Rec->getValueAsBitsInit("Opcode"));
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StringRef Name = Rec->getName();
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const CodeGenInstruction *NewInst = nullptr;
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if (ManualMap.find(Name) != ManualMap.end()) {
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Record *NewRec = Records.getDef(ManualMap.at(Rec->getName()));
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assert(NewRec && "Instruction not found!");
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NewInst = &Target.getInstruction(NewRec);
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} else if (Name.ends_with("_EVEX")) {
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if (auto *NewRec = Records.getDef(Name.drop_back(5)))
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NewInst = &Target.getInstruction(NewRec);
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} else if (Name.ends_with("_ND")) {
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if (auto *NewRec = Records.getDef(Name.drop_back(3))) {
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auto &TempInst = Target.getInstruction(NewRec);
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if (isRegisterOperand(TempInst.Operands[0].Rec))
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NewInst = &TempInst;
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}
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} else {
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// For each pre-compression instruction look for a match in the appropriate
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// vector (instructions with the same opcode) using function object
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// IsMatch.
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auto Match = llvm::find_if(CompressedInsts[Opcode], IsMatch(Inst));
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if (Match != CompressedInsts[Opcode].end())
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NewInst = *Match;
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}
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if (!NewInst)
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continue;
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Table.push_back(std::make_pair(Inst, NewInst));
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auto Predicates = NewInst->TheDef->getValueAsListOfDefs("Predicates");
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auto It = llvm::find_if(Predicates, [](const Record *R) {
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StringRef Name = R->getName();
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return Name == "HasAVXNECONVERT" || Name == "HasAVXVNNI" ||
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Name == "HasAVXIFMA";
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});
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if(It!= Predicates.end())
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PredicateInsts[*It].push_back(NewInst);
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}
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printTable(Table, OS);
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printCheckPredicate(PredicateInsts, OS);
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}
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} // namespace
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static TableGen::Emitter::OptClass<X86CompressEVEXTablesEmitter>
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X("gen-x86-compress-evex-tables", "Generate X86 EVEX compression tables");
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