74 lines
2.4 KiB
MLIR
74 lines
2.4 KiB
MLIR
// RUN: mlir-opt -split-input-file -convert-gpu-to-spirv -verify-diagnostics %s -o - | FileCheck %s
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module attributes {
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gpu.container_module,
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spirv.target_env = #spirv.target_env<#spirv.vce<v1.4, [Shader, GroupNonUniformShuffle], []>, #spirv.resource_limits<subgroup_size = 16>>
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} {
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gpu.module @kernels {
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// CHECK-LABEL: spirv.func @shuffle_xor()
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gpu.func @shuffle_xor() kernel
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attributes {spirv.entry_point_abi = #spirv.entry_point_abi<workgroup_size = [16, 1, 1]>} {
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%mask = arith.constant 8 : i32
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%width = arith.constant 16 : i32
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%val = arith.constant 42.0 : f32
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// CHECK: %[[MASK:.+]] = spirv.Constant 8 : i32
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// CHECK: %[[VAL:.+]] = spirv.Constant 4.200000e+01 : f32
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// CHECK: %{{.+}} = spirv.Constant true
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// CHECK: %{{.+}} = spirv.GroupNonUniformShuffleXor <Subgroup> %[[VAL]], %[[MASK]] : f32, i32
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%result, %valid = gpu.shuffle xor %val, %mask, %width : f32
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gpu.return
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}
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}
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}
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// -----
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module attributes {
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gpu.container_module,
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spirv.target_env = #spirv.target_env<#spirv.vce<v1.4, [Shader, GroupNonUniformShuffle], []>, #spirv.resource_limits<subgroup_size = 32>>
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} {
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gpu.module @kernels {
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gpu.func @shuffle_xor() kernel
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attributes {spirv.entry_point_abi = #spirv.entry_point_abi<workgroup_size = [16, 1, 1]>} {
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%mask = arith.constant 8 : i32
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%width = arith.constant 16 : i32
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%val = arith.constant 42.0 : f32
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// Cannot convert due to shuffle width and target subgroup size mismatch
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// expected-error @+1 {{failed to legalize operation 'gpu.shuffle'}}
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%result, %valid = gpu.shuffle xor %val, %mask, %width : f32
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gpu.return
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}
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}
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}
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// -----
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module attributes {
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gpu.container_module,
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spirv.target_env = #spirv.target_env<#spirv.vce<v1.4, [Shader, GroupNonUniformShuffle], []>, #spirv.resource_limits<subgroup_size = 16>>
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} {
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gpu.module @kernels {
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// CHECK-LABEL: spirv.func @shuffle_idx()
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gpu.func @shuffle_idx() kernel
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attributes {spirv.entry_point_abi = #spirv.entry_point_abi<workgroup_size = [16, 1, 1]>} {
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%mask = arith.constant 8 : i32
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%width = arith.constant 16 : i32
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%val = arith.constant 42.0 : f32
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// CHECK: %[[MASK:.+]] = spirv.Constant 8 : i32
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// CHECK: %[[VAL:.+]] = spirv.Constant 4.200000e+01 : f32
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// CHECK: %{{.+}} = spirv.Constant true
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// CHECK: %{{.+}} = spirv.GroupNonUniformShuffle <Subgroup> %[[VAL]], %[[MASK]] : f32, i32
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%result, %valid = gpu.shuffle idx %val, %mask, %width : f32
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gpu.return
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}
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}
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}
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