76 lines
No EOL
2.5 KiB
C++
76 lines
No EOL
2.5 KiB
C++
//===- TestNVGPUTransforms.cpp - Test NVGPU transforms and lowerings ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include <type_traits>
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#include "mlir/Analysis/SliceAnalysis.h"
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#include "mlir/Dialect/Affine/IR/AffineOps.h"
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#include "mlir/Dialect/Func/IR/FuncOps.h"
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#include "mlir/Dialect/GPU/IR/GPUDialect.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/Dialect/Linalg/IR/Linalg.h"
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#include "mlir/Dialect/Linalg/Passes.h"
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#include "mlir/Dialect/Linalg/Transforms/Transforms.h"
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#include "mlir/Dialect/MemRef/IR/MemRef.h"
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#include "mlir/Dialect/NVGPU/Transforms/Transforms.h"
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#include "mlir/Dialect/SCF/IR/SCF.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Pass/PassManager.h"
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#include "mlir/Support/LLVM.h"
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#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
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using namespace mlir;
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using namespace mlir::nvgpu;
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namespace {
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struct TestMmaSyncF32ToTF32Patterns
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: public PassWrapper<TestMmaSyncF32ToTF32Patterns,
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OperationPass<func::FuncOp>> {
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MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(TestMmaSyncF32ToTF32Patterns)
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StringRef getArgument() const final {
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return "test-nvgpu-mmasync-f32-to-tf32-patterns";
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}
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StringRef getDescription() const final {
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return "Test patterns to convert mma.sync on f32 with tf32 precision";
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}
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TestMmaSyncF32ToTF32Patterns() = default;
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TestMmaSyncF32ToTF32Patterns(const TestMmaSyncF32ToTF32Patterns &pass)
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: PassWrapper(pass) {}
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Option<std::string> precision{
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*this, "precision",
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llvm::cl::desc(
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"Target nvgpu.mma.sync on f32 input with tf32 or tf32x3 precision"),
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llvm::cl::init("tf32")};
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MmaSyncF32Lowering tf32Precision =
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llvm::StringSwitch<MmaSyncF32Lowering>(precision)
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.Case("tf32", MmaSyncF32Lowering::TF32)
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.Case("tf32x3", MmaSyncF32Lowering::TF32x3)
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.Default(MmaSyncF32Lowering::Unkown);
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void runOnOperation() override {
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RewritePatternSet patterns(&getContext());
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populateMmaSyncF32ToTF32Patterns(patterns, tf32Precision);
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(void)applyPatternsAndFoldGreedily(getOperation(), std::move(patterns));
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}
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};
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} // namespace
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namespace mlir {
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namespace test {
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void registerTestNvgpuLowerings() {
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PassRegistration<TestMmaSyncF32ToTF32Patterns>();
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}
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} // namespace test
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} // namespace mlir
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