222 lines
7.4 KiB
Text
222 lines
7.4 KiB
Text
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV32
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# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=instruction-select \
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# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV64
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---
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name: float_imm
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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; RV32-LABEL: name: float_imm
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; RV32: [[LUI:%[0-9]+]]:gpr = LUI 263313
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; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -37
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; RV32-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[ADDI]]
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; RV32-NEXT: $f10_f = COPY [[FMV_W_X]]
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; RV32-NEXT: PseudoRET implicit $f10_f
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;
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; RV64-LABEL: name: float_imm
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; RV64: [[LUI:%[0-9]+]]:gpr = LUI 263313
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; RV64-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -37
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; RV64-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[ADDIW]]
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; RV64-NEXT: $f10_f = COPY [[FMV_W_X]]
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; RV64-NEXT: PseudoRET implicit $f10_f
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%0:fprb(s32) = G_FCONSTANT float 0x400921FB60000000
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$f10_f = COPY %0(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: float_imm_op
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $f10_f
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; CHECK-LABEL: name: float_imm_op
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; CHECK: liveins: $f10_f
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
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; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 260096
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; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[LUI]]
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; CHECK-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[COPY]], [[FMV_W_X]], 7
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; CHECK-NEXT: $f10_f = COPY [[FADD_S]]
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; CHECK-NEXT: PseudoRET implicit $f10_f
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%0:fprb(s32) = COPY $f10_f
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%1:fprb(s32) = G_FCONSTANT float 1.000000e+00
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%2:fprb(s32) = G_FADD %0, %1
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$f10_f = COPY %2(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: float_positive_zero
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $x10
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; CHECK-LABEL: name: float_positive_zero
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
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; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[COPY]]
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; CHECK-NEXT: $f10_f = COPY [[FMV_W_X]]
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; CHECK-NEXT: PseudoRET implicit $f10_f
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%1:fprb(s32) = G_FCONSTANT float 0.000000e+00
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$f10_f = COPY %1(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: float_negative_zero
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $x10
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; CHECK-LABEL: name: float_negative_zero
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; CHECK: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
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; CHECK-NEXT: [[FMV_W_X:%[0-9]+]]:fpr32 = FMV_W_X [[LUI]]
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; CHECK-NEXT: $f10_f = COPY [[FMV_W_X]]
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; CHECK-NEXT: PseudoRET implicit $f10_f
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%1:fprb(s32) = G_FCONSTANT float -0.000000e+00
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$f10_f = COPY %1(s32)
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PseudoRET implicit $f10_f
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...
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---
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name: double_imm
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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; RV32-LABEL: name: double_imm
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; RV32: [[LUI:%[0-9]+]]:gpr = LUI 262290
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; RV32-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], 507
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; RV32-NEXT: [[LUI1:%[0-9]+]]:gpr = LUI 345155
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; RV32-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[LUI1]], -744
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; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[ADDI1]], [[ADDI]]
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; RV32-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]]
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; RV32-NEXT: PseudoRET implicit $f10_d
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;
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; RV64-LABEL: name: double_imm
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; RV64: [[LUI:%[0-9]+]]:gpr = LUI 512
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; RV64-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], 1169
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; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDIW]], 15
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; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[SLLI]], -299
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; RV64-NEXT: [[SLLI1:%[0-9]+]]:gpr = SLLI [[ADDI]], 14
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; RV64-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[SLLI1]], 1091
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; RV64-NEXT: [[SLLI2:%[0-9]+]]:gpr = SLLI [[ADDI1]], 12
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; RV64-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI [[SLLI2]], -744
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; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[ADDI2]]
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; RV64-NEXT: $f10_d = COPY [[FMV_D_X]]
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; RV64-NEXT: PseudoRET implicit $f10_d
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%0:fprb(s64) = G_FCONSTANT double 0x400921FB54442D18
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$f10_d = COPY %0(s64)
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PseudoRET implicit $f10_d
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...
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---
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name: double_imm_op
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $f10_d
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; RV32-LABEL: name: double_imm_op
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; RV32: liveins: $f10_d
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; RV32-NEXT: {{ $}}
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; RV32-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
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; RV32-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 261888
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; RV32-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
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; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY1]], [[LUI]]
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; RV32-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[BuildPairF64Pseudo]], 7
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; RV32-NEXT: $f10_d = COPY [[FADD_D]]
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; RV32-NEXT: PseudoRET implicit $f10_d
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;
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; RV64-LABEL: name: double_imm_op
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; RV64: liveins: $f10_d
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; RV64-NEXT: {{ $}}
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; RV64-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $f10_d
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; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1023
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; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 52
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; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[SLLI]]
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; RV64-NEXT: [[FADD_D:%[0-9]+]]:fpr64 = nofpexcept FADD_D [[COPY]], [[FMV_D_X]], 7
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; RV64-NEXT: $f10_d = COPY [[FADD_D]]
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; RV64-NEXT: PseudoRET implicit $f10_d
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%0:fprb(s64) = COPY $f10_d
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%1:fprb(s64) = G_FCONSTANT double 1.000000e+00
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%2:fprb(s64) = G_FADD %0, %1
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$f10_d = COPY %2(s64)
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PseudoRET implicit $f10_d
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...
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---
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name: double_positive_zero
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $x10
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; RV32-LABEL: name: double_positive_zero
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; RV32: liveins: $x10
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; RV32-NEXT: {{ $}}
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; RV32-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
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; RV32-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x0
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; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY1]], [[COPY]]
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; RV32-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]]
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; RV32-NEXT: PseudoRET implicit $f10_d
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;
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; RV64-LABEL: name: double_positive_zero
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; RV64: liveins: $x10
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; RV64-NEXT: {{ $}}
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; RV64-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
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; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[COPY]]
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; RV64-NEXT: $f10_d = COPY [[FMV_D_X]]
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; RV64-NEXT: PseudoRET implicit $f10_d
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%1:fprb(s64) = G_FCONSTANT double 0.000000e+00
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$f10_d = COPY %1(s64)
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PseudoRET implicit $f10_d
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...
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---
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name: double_negative_zero
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legalized: true
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regBankSelected: true
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body: |
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bb.1:
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liveins: $x10
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; RV32-LABEL: name: double_negative_zero
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; RV32: liveins: $x10
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; RV32-NEXT: {{ $}}
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; RV32-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524288
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; RV32-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
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; RV32-NEXT: [[BuildPairF64Pseudo:%[0-9]+]]:fpr64 = BuildPairF64Pseudo [[COPY]], [[LUI]]
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; RV32-NEXT: $f10_d = COPY [[BuildPairF64Pseudo]]
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; RV32-NEXT: PseudoRET implicit $f10_d
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;
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; RV64-LABEL: name: double_negative_zero
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; RV64: liveins: $x10
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; RV64-NEXT: {{ $}}
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; RV64-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
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; RV64-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 63
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; RV64-NEXT: [[FMV_D_X:%[0-9]+]]:fpr64 = FMV_D_X [[SLLI]]
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; RV64-NEXT: $f10_d = COPY [[FMV_D_X]]
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; RV64-NEXT: PseudoRET implicit $f10_d
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%1:fprb(s64) = G_FCONSTANT double -0.000000e+00
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$f10_d = COPY %1(s64)
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PseudoRET implicit $f10_d
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...
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