332 lines
12 KiB
C++
332 lines
12 KiB
C++
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//===-- RISCVInstPrinter.cpp - Convert RISC-V MCInst to asm syntax --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an RISC-V MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVInstPrinter.h"
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#include "RISCVBaseInfo.h"
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#include "RISCVMCExpr.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstPrinter.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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// Include the auto-generated portion of the assembly writer.
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#define PRINT_ALIAS_INSTR
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#include "RISCVGenAsmWriter.inc"
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static cl::opt<bool>
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NoAliases("riscv-no-aliases",
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cl::desc("Disable the emission of assembler pseudo instructions"),
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cl::init(false), cl::Hidden);
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// Print architectural register names rather than the ABI names (such as x2
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// instead of sp).
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// TODO: Make RISCVInstPrinter::getRegisterName non-static so that this can a
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// member.
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static bool ArchRegNames;
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// The command-line flags above are used by llvm-mc and llc. They can be used by
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// `llvm-objdump`, but we override their values here to handle options passed to
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// `llvm-objdump` with `-M` (which matches GNU objdump). There did not seem to
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// be an easier way to allow these options in all these tools, without doing it
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// this way.
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bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
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if (Opt == "no-aliases") {
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PrintAliases = false;
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return true;
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}
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if (Opt == "numeric") {
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ArchRegNames = true;
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return true;
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}
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return false;
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}
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void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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StringRef Annot, const MCSubtargetInfo &STI,
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raw_ostream &O) {
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bool Res = false;
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const MCInst *NewMI = MI;
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MCInst UncompressedMI;
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if (PrintAliases && !NoAliases)
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Res = RISCVRVC::uncompress(UncompressedMI, *MI, STI);
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if (Res)
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NewMI = const_cast<MCInst *>(&UncompressedMI);
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if (!PrintAliases || NoAliases || !printAliasInstr(NewMI, Address, STI, O))
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printInstruction(NewMI, Address, STI, O);
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printAnnotation(O, Annot);
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}
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void RISCVInstPrinter::printRegName(raw_ostream &O, MCRegister Reg) const {
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markup(O, Markup::Register) << getRegisterName(Reg);
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}
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void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O,
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const char *Modifier) {
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assert((Modifier == nullptr || Modifier[0] == 0) && "No modifiers supported");
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const MCOperand &MO = MI->getOperand(OpNo);
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if (MO.isReg()) {
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printRegName(O, MO.getReg());
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return;
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}
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if (MO.isImm()) {
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markup(O, Markup::Immediate) << formatImm(MO.getImm());
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return;
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}
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assert(MO.isExpr() && "Unknown operand kind in printOperand");
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MO.getExpr()->print(O, &MAI);
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}
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void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
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unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNo);
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if (!MO.isImm())
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return printOperand(MI, OpNo, STI, O);
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if (PrintBranchImmAsAddress) {
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uint64_t Target = Address + MO.getImm();
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if (!STI.hasFeature(RISCV::Feature64Bit))
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Target &= 0xffffffff;
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markup(O, Markup::Target) << formatHex(Target);
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} else {
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markup(O, Markup::Target) << formatImm(MO.getImm());
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}
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}
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void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned Imm = MI->getOperand(OpNo).getImm();
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auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
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if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
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markup(O, Markup::Register) << SysReg->Name;
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else
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markup(O, Markup::Register) << formatImm(Imm);
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}
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void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned FenceArg = MI->getOperand(OpNo).getImm();
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assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
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if ((FenceArg & RISCVFenceField::I) != 0)
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O << 'i';
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if ((FenceArg & RISCVFenceField::O) != 0)
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O << 'o';
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if ((FenceArg & RISCVFenceField::R) != 0)
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O << 'r';
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if ((FenceArg & RISCVFenceField::W) != 0)
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O << 'w';
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if (FenceArg == 0)
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O << "0";
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}
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void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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auto FRMArg =
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static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
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if (PrintAliases && !NoAliases && FRMArg == RISCVFPRndMode::RoundingMode::DYN)
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return;
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O << ", " << RISCVFPRndMode::roundingModeToString(FRMArg);
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}
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void RISCVInstPrinter::printFRMArgLegacy(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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auto FRMArg =
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static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
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// Never print rounding mode if it's the default 'rne'. This ensures the
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// output can still be parsed by older tools that erroneously failed to
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// accept a rounding mode.
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if (FRMArg == RISCVFPRndMode::RoundingMode::RNE)
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return;
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O << ", " << RISCVFPRndMode::roundingModeToString(FRMArg);
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}
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void RISCVInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned Imm = MI->getOperand(OpNo).getImm();
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if (Imm == 1) {
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markup(O, Markup::Immediate) << "min";
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} else if (Imm == 30) {
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markup(O, Markup::Immediate) << "inf";
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} else if (Imm == 31) {
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markup(O, Markup::Immediate) << "nan";
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} else {
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float FPVal = RISCVLoadFPImm::getFPImm(Imm);
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// If the value is an integer, print a .0 fraction. Otherwise, use %g to
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// which will not print trailing zeros and will use scientific notation
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// if it is shorter than printing as a decimal. The smallest value requires
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// 12 digits of precision including the decimal.
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if (FPVal == (int)(FPVal))
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markup(O, Markup::Immediate) << format("%.1f", FPVal);
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else
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markup(O, Markup::Immediate) << format("%.12g", FPVal);
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}
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}
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void RISCVInstPrinter::printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNo);
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assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands");
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O << "(";
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printRegName(O, MO.getReg());
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O << ")";
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}
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void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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unsigned Imm = MI->getOperand(OpNo).getImm();
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// Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
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// or non-zero in bits 8 and above.
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if (RISCVVType::getVLMUL(Imm) == RISCVII::VLMUL::LMUL_RESERVED ||
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RISCVVType::getSEW(Imm) > 64 || (Imm >> 8) != 0) {
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O << formatImm(Imm);
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return;
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}
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// Print the text form.
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RISCVVType::printVType(Imm, O);
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}
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void RISCVInstPrinter::printRlist(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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unsigned Imm = MI->getOperand(OpNo).getImm();
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O << "{";
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switch (Imm) {
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case RISCVZC::RLISTENCODE::RA:
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markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
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break;
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case RISCVZC::RLISTENCODE::RA_S0:
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markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
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O << ", ";
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markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
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break;
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case RISCVZC::RLISTENCODE::RA_S0_S1:
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markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
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O << ", ";
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markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
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O << '-';
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markup(O, Markup::Register) << (ArchRegNames ? "x9" : "s1");
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break;
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case RISCVZC::RLISTENCODE::RA_S0_S2:
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markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
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O << ", ";
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markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
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O << '-';
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markup(O, Markup::Register) << (ArchRegNames ? "x9" : "s2");
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if (ArchRegNames) {
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O << ", ";
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markup(O, Markup::Register) << "x18";
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}
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break;
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case RISCVZC::RLISTENCODE::RA_S0_S3:
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case RISCVZC::RLISTENCODE::RA_S0_S4:
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case RISCVZC::RLISTENCODE::RA_S0_S5:
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case RISCVZC::RLISTENCODE::RA_S0_S6:
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case RISCVZC::RLISTENCODE::RA_S0_S7:
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case RISCVZC::RLISTENCODE::RA_S0_S8:
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case RISCVZC::RLISTENCODE::RA_S0_S9:
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case RISCVZC::RLISTENCODE::RA_S0_S11:
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markup(O, Markup::Register) << (ArchRegNames ? "x1" : "ra");
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O << ", ";
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markup(O, Markup::Register) << (ArchRegNames ? "x8" : "s0");
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O << '-';
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if (ArchRegNames) {
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markup(O, Markup::Register) << "x9";
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O << ", ";
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markup(O, Markup::Register) << "x18";
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O << '-';
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}
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markup(O, Markup::Register) << getRegisterName(
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RISCV::X19 + (Imm == RISCVZC::RLISTENCODE::RA_S0_S11
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? 8
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: Imm - RISCVZC::RLISTENCODE::RA_S0_S3));
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break;
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default:
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llvm_unreachable("invalid register list");
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}
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O << "}";
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}
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void RISCVInstPrinter::printRegReg(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNo);
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assert(MO.isReg() && "printRegReg can only print register operands");
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if (MO.getReg() == RISCV::NoRegister)
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return;
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printRegName(O, MO.getReg());
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O << "(";
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const MCOperand &MO1 = MI->getOperand(OpNo + 1);
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assert(MO1.isReg() && "printRegReg can only print register operands");
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printRegName(O, MO1.getReg());
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O << ")";
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}
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void RISCVInstPrinter::printSpimm(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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int64_t Imm = MI->getOperand(OpNo).getImm();
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unsigned Opcode = MI->getOpcode();
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bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
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bool IsEABI = STI.hasFeature(RISCV::FeatureRVE);
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int64_t Spimm = 0;
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auto RlistVal = MI->getOperand(0).getImm();
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assert(RlistVal != 16 && "Incorrect rlist.");
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auto Base = RISCVZC::getStackAdjBase(RlistVal, IsRV64, IsEABI);
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Spimm = Imm + Base;
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assert((Spimm >= Base && Spimm <= Base + 48) && "Incorrect spimm");
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if (Opcode == RISCV::CM_PUSH)
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Spimm = -Spimm;
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// RAII guard for ANSI color escape sequences
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WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
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RISCVZC::printSpimm(Spimm, O);
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}
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void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand(OpNo);
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assert(MO.isReg() && "printVMaskReg can only print register operands");
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if (MO.getReg() == RISCV::NoRegister)
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return;
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O << ", ";
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printRegName(O, MO.getReg());
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O << ".t";
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}
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const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
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return getRegisterName(Reg, ArchRegNames ? RISCV::NoRegAltName
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: RISCV::ABIRegAltName);
|
||
|
|
}
|