28 lines
940 B
TableGen
28 lines
940 B
TableGen
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//=- RISCVCombine.td - Define RISC-V Combine Rules -----------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/GlobalISel/Combine.td"
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def RISCVPreLegalizerCombiner: GICombiner<
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"RISCVPreLegalizerCombinerImpl", [all_combines]> {
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}
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def RISCVO0PreLegalizerCombiner: GICombiner<
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"RISCVO0PreLegalizerCombinerImpl", [optnone_combines]> {
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}
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// Post-legalization combines which are primarily optimizations.
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// TODO: Add more combines.
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def RISCVPostLegalizerCombiner
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: GICombiner<"RISCVPostLegalizerCombinerImpl",
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[redundant_and, identity_combines]> {
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}
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