707 lines
30 KiB
TableGen
707 lines
30 KiB
TableGen
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//===-- RISCVInstrInfoXCV.td - CORE-V instructions ---------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the vendor extensions defined by Core-V extensions.
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//
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "XCVbitmanip" in {
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class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInstIBase<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
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bits<5> is3;
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bits<5> is2;
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let Inst{31-30} = funct2;
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let Inst{29-25} = is3;
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let Inst{24-20} = is2;
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}
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class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr,
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Operand i3type = uimm5>
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: CVInstBitManipRII<funct2, funct3, (outs GPR:$rd),
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(ins GPR:$rs1, i3type:$is3, uimm5:$is2),
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opcodestr, "$rd, $rs1, $is3, $is2">;
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class CVBitManipRR<bits<7> funct7, string opcodestr>
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: RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
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(ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
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class CVBitManipR<bits<7> funct7, string opcodestr>
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: RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd),
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(ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
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let rs2 = 0b00000;
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}
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}
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let Predicates = [HasVendorXCVbitmanip, IsRV32],
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hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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def CV_EXTRACT : CVBitManipRII<0b00, 0b000, "cv.extract">;
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def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">;
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def CV_BCLR : CVBitManipRII<0b00, 0b001, "cv.bclr">;
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def CV_BSET : CVBitManipRII<0b01, 0b001, "cv.bset">;
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def CV_BITREV : CVBitManipRII<0b11, 0b001, "cv.bitrev", uimm2>;
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def CV_EXTRACTR : CVBitManipRR<0b0011000, "cv.extractr">;
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def CV_EXTRACTUR : CVBitManipRR<0b0011001, "cv.extractur">;
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let Constraints = "$rd = $rd_wb" in {
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def CV_INSERT : CVInstBitManipRII<0b10, 0b000, (outs GPR:$rd_wb),
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(ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
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"cv.insert", "$rd, $rs1, $is3, $is2">;
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def CV_INSERTR : RVInstR<0b0011010, 0b011, OPC_CUSTOM_1, (outs GPR:$rd_wb),
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(ins GPR:$rd, GPR:$rs1, GPR:$rs2),
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"cv.insertr", "$rd, $rs1, $rs2">;
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}
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def CV_BCLRR : CVBitManipRR<0b0011100, "cv.bclrr">;
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def CV_BSETR : CVBitManipRR<0b0011101, "cv.bsetr">;
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def CV_ROR : CVBitManipRR<0b0100000, "cv.ror">;
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def CV_FF1 : CVBitManipR<0b0100001, "cv.ff1">;
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def CV_FL1 : CVBitManipR<0b0100010, "cv.fl1">;
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def CV_CLB : CVBitManipR<0b0100011, "cv.clb">;
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def CV_CNT : CVBitManipR<0b0100100, "cv.cnt">;
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}
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class CVInstMac<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstR<funct7, funct3, OPC_CUSTOM_1,
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(outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
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opcodestr, "$rd, $rs1, $rs2"> {
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let DecoderNamespace = "XCVmac";
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}
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class CVInstMacMulN<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
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string opcodestr>
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: RVInstRBase<funct3, OPC_CUSTOM_2, outs, ins, opcodestr,
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"$rd, $rs1, $rs2, $imm5"> {
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bits<5> imm5;
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let Inst{31-30} = funct2;
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let Inst{29-25} = imm5;
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let DecoderNamespace = "XCVmac";
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}
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class CVInstMacN<bits<2> funct2, bits<3> funct3, string opcodestr>
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: CVInstMacMulN<funct2, funct3, (outs GPR:$rd_wb),
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(ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
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class CVInstMulN<bits<2> funct2, bits<3> funct3, string opcodestr>
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: CVInstMacMulN<funct2, funct3, (outs GPR:$rd),
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(ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
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let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0,
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mayStore = 0, Constraints = "$rd = $rd_wb" in {
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// 32x32 bit macs
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def CV_MAC : CVInstMac<0b1001000, 0b011, "cv.mac">,
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Sched<[]>;
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def CV_MSU : CVInstMac<0b1001001, 0b011, "cv.msu">,
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Sched<[]>;
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// Signed 16x16 bit macs with imm
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def CV_MACSN : CVInstMacN<0b00, 0b110, "cv.macsn">,
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Sched<[]>;
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def CV_MACHHSN : CVInstMacN<0b01, 0b110, "cv.machhsn">,
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Sched<[]>;
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def CV_MACSRN : CVInstMacN<0b10, 0b110, "cv.macsrn">,
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Sched<[]>;
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def CV_MACHHSRN : CVInstMacN<0b11, 0b110, "cv.machhsrn">,
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Sched<[]>;
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// Unsigned 16x16 bit macs with imm
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def CV_MACUN : CVInstMacN<0b00, 0b111, "cv.macun">,
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Sched<[]>;
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def CV_MACHHUN : CVInstMacN<0b01, 0b111, "cv.machhun">,
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Sched<[]>;
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def CV_MACURN : CVInstMacN<0b10, 0b111, "cv.macurn">,
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Sched<[]>;
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def CV_MACHHURN : CVInstMacN<0b11, 0b111, "cv.machhurn">,
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Sched<[]>;
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} // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0...
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let Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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// Signed 16x16 bit muls with imm
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def CV_MULSN : CVInstMulN<0b00, 0b100, "cv.mulsn">,
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Sched<[]>;
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def CV_MULHHSN : CVInstMulN<0b01, 0b100, "cv.mulhhsn">,
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Sched<[]>;
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def CV_MULSRN : CVInstMulN<0b10, 0b100, "cv.mulsrn">,
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Sched<[]>;
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def CV_MULHHSRN : CVInstMulN<0b11, 0b100, "cv.mulhhsrn">,
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Sched<[]>;
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// Unsigned 16x16 bit muls with imm
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def CV_MULUN : CVInstMulN<0b00, 0b101, "cv.mulun">,
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Sched<[]>;
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def CV_MULHHUN : CVInstMulN<0b01, 0b101, "cv.mulhhun">,
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Sched<[]>;
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def CV_MULURN : CVInstMulN<0b10, 0b101, "cv.mulurn">,
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Sched<[]>;
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def CV_MULHHURN : CVInstMulN<0b11, 0b101, "cv.mulhhurn">,
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Sched<[]>;
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} // Predicates = [HasVendorXCVmac, IsRV32], hasSideEffects = 0, mayLoad = 0...
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let Predicates = [HasVendorXCVmac, IsRV32] in {
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// Xcvmac Pseudo Instructions
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// Signed 16x16 bit muls
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def : InstAlias<"cv.muls $rd1, $rs1, $rs2",
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(CV_MULSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
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def : InstAlias<"cv.mulhhs $rd1, $rs1, $rs2",
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(CV_MULHHSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
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// Unsigned 16x16 bit muls
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def : InstAlias<"cv.mulu $rd1, $rs1, $rs2",
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(CV_MULUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
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def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2",
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(CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
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} // Predicates = [HasVendorXCVmac, IsRV32]
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let DecoderNamespace = "XCValu" in {
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class CVInstAluRRI<bits<2> funct2, bits<3> funct3, string opcodestr>
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: RVInstRBase<funct3, OPC_CUSTOM_2, (outs GPR:$rd),
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(ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr,
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"$rd, $rs1, $rs2, $imm5"> {
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bits<5> imm5;
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let Inst{31-30} = funct2;
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let Inst{29-25} = imm5;
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}
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class CVInstAluRR<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd),
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(ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
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class CVInstAluRRNR<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd_wb),
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(ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
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class CVInstAluRI<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstIBase<funct3, OPC_CUSTOM_1, (outs GPR:$rd),
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(ins GPR:$rs1, uimm5:$imm5), opcodestr,
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"$rd, $rs1, $imm5"> {
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bits<5> imm5;
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let Inst{31-25} = funct7;
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let Inst{24-20} = imm5;
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}
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class CVInstAluR<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins GPR:$rs1),
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opcodestr, "$rd, $rs1"> {
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let rs2 = 0b00000;
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}
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} // DecoderNamespace = "XCValu"
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let Predicates = [HasVendorXCValu],
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hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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// General ALU Operations
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def CV_ABS : CVInstAluR<0b0101000, 0b011, "cv.abs">,
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Sched<[]>;
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def CV_SLET : CVInstAluRR<0b0101001, 0b011, "cv.slet">,
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Sched<[]>;
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def CV_SLETU : CVInstAluRR<0b0101010, 0b011, "cv.sletu">,
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Sched<[]>;
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def CV_MIN : CVInstAluRR<0b0101011, 0b011, "cv.min">,
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Sched<[]>;
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def CV_MINU : CVInstAluRR<0b0101100, 0b011, "cv.minu">,
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Sched<[]>;
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def CV_MAX : CVInstAluRR<0b0101101, 0b011, "cv.max">,
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Sched<[]>;
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def CV_MAXU : CVInstAluRR<0b0101110, 0b011, "cv.maxu">,
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Sched<[]>;
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def CV_EXTHS : CVInstAluR<0b0110000, 0b011, "cv.exths">,
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Sched<[]>;
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def CV_EXTHZ : CVInstAluR<0b0110001, 0b011, "cv.exthz">,
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Sched<[]>;
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def CV_EXTBS : CVInstAluR<0b0110010, 0b011, "cv.extbs">,
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Sched<[]>;
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def CV_EXTBZ : CVInstAluR<0b0110011, 0b011, "cv.extbz">,
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Sched<[]>;
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def CV_CLIP : CVInstAluRI<0b0111000, 0b011, "cv.clip">,
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Sched<[]>;
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def CV_CLIPU : CVInstAluRI<0b0111001, 0b011, "cv.clipu">,
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Sched<[]>;
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def CV_CLIPR : CVInstAluRR<0b0111010, 0b011, "cv.clipr">,
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Sched<[]>;
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def CV_CLIPUR : CVInstAluRR<0b0111011, 0b011, "cv.clipur">,
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Sched<[]>;
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def CV_ADDN : CVInstAluRRI<0b00, 0b010, "cv.addn">,
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Sched<[]>;
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def CV_ADDUN : CVInstAluRRI<0b01, 0b010, "cv.addun">,
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Sched<[]>;
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def CV_ADDRN : CVInstAluRRI<0b10, 0b010, "cv.addrn">,
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Sched<[]>;
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def CV_ADDURN : CVInstAluRRI<0b11, 0b010, "cv.addurn">,
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Sched<[]>;
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def CV_SUBN : CVInstAluRRI<0b00, 0b011, "cv.subn">,
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Sched<[]>;
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def CV_SUBUN : CVInstAluRRI<0b01, 0b011, "cv.subun">,
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Sched<[]>;
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def CV_SUBRN : CVInstAluRRI<0b10, 0b011, "cv.subrn">,
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Sched<[]>;
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def CV_SUBURN : CVInstAluRRI<0b11, 0b011, "cv.suburn">,
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Sched<[]>;
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} // Predicates = [HasVendorXCValu],
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// hasSideEffects = 0, mayLoad = 0, mayStore = 0
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let Predicates = [HasVendorXCValu],
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hasSideEffects = 0, mayLoad = 0, mayStore = 0,
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Constraints = "$rd = $rd_wb" in {
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def CV_ADDNR : CVInstAluRRNR<0b1000000, 0b011, "cv.addnr">,
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Sched<[]>;
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def CV_ADDUNR : CVInstAluRRNR<0b1000001, 0b011, "cv.addunr">,
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Sched<[]>;
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def CV_ADDRNR : CVInstAluRRNR<0b1000010, 0b011, "cv.addrnr">,
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Sched<[]>;
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def CV_ADDURNR : CVInstAluRRNR<0b1000011, 0b011, "cv.addurnr">,
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Sched<[]>;
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def CV_SUBNR : CVInstAluRRNR<0b1000100, 0b011, "cv.subnr">,
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Sched<[]>;
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def CV_SUBUNR : CVInstAluRRNR<0b1000101, 0b011, "cv.subunr">,
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Sched<[]>;
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def CV_SUBRNR : CVInstAluRRNR<0b1000110, 0b011, "cv.subrnr">,
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Sched<[]>;
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def CV_SUBURNR : CVInstAluRRNR<0b1000111, 0b011, "cv.suburnr">,
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Sched<[]>;
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} // Predicates = [HasVendorXCValu],
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// hasSideEffects = 0, mayLoad = 0, mayStore = 0,
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// Constraints = "$rd = $rd_wb"
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class CVInstSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
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RISCVOpcode opcode, dag outs,
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dag ins, string opcodestr, string argstr>
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||
|
|
: RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {
|
||
|
|
let Inst{31-27} = funct5;
|
||
|
|
let Inst{26} = F;
|
||
|
|
let Inst{25} = funct1;
|
||
|
|
let DecoderNamespace = "XCVsimd";
|
||
|
|
}
|
||
|
|
|
||
|
|
class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode,
|
||
|
|
dag outs, dag ins, string opcodestr, string argstr>
|
||
|
|
: RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
|
||
|
|
bits<6> imm6;
|
||
|
|
|
||
|
|
let Inst{31-27} = funct5;
|
||
|
|
let Inst{26} = F;
|
||
|
|
let Inst{25} = imm6{0}; // funct1 unused
|
||
|
|
let Inst{24-20} = imm6{5-1};
|
||
|
|
let DecoderNamespace = "XCVsimd";
|
||
|
|
}
|
||
|
|
|
||
|
|
class CVSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
|
||
|
|
string opcodestr>
|
||
|
|
: CVInstSIMDRR<funct5, F, funct1, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
|
||
|
|
(ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
|
||
|
|
|
||
|
|
class CVSIMDRRWb<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
|
||
|
|
string opcodestr>
|
||
|
|
: CVInstSIMDRR<funct5, F, funct1, funct3, OPC_CUSTOM_3, (outs GPR:$rd_wb),
|
||
|
|
(ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
|
||
|
|
let Constraints = "$rd = $rd_wb";
|
||
|
|
}
|
||
|
|
|
||
|
|
class CVSIMDRI<bits<5> funct5, bit F, bits<3> funct3, string opcodestr>
|
||
|
|
: CVInstSIMDRI<funct5, F, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
|
||
|
|
(ins GPR:$rs1, simm6:$imm6), opcodestr, "$rd, $rs1, $imm6">;
|
||
|
|
|
||
|
|
class CVSIMDRIWb<bits<5> funct5, bit F, bits<3> funct3, string opcodestr>
|
||
|
|
: CVInstSIMDRI<funct5, F, funct3, OPC_CUSTOM_3,
|
||
|
|
(outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, simm6:$imm6),
|
||
|
|
opcodestr, "$rd, $rs1, $imm6"> {
|
||
|
|
let Constraints = "$rd = $rd_wb";
|
||
|
|
}
|
||
|
|
|
||
|
|
class CVSIMDRU<bits<5> funct5, bit F, bits<3> funct3, string opcodestr,
|
||
|
|
Operand immtype = uimm6>
|
||
|
|
: CVInstSIMDRI<funct5, F, funct3, OPC_CUSTOM_3,
|
||
|
|
(outs GPR:$rd), (ins GPR:$rs1, immtype:$imm6),
|
||
|
|
opcodestr, "$rd, $rs1, $imm6">;
|
||
|
|
|
||
|
|
class CVSIMDRUWb<bits<5> funct5, bit F, bits<3> funct3, string opcodestr>
|
||
|
|
: CVInstSIMDRI<funct5, F, funct3, OPC_CUSTOM_3,
|
||
|
|
(outs GPR:$rd_wb),
|
||
|
|
(ins GPR:$rd, GPR:$rs1, uimm6:$imm6),
|
||
|
|
opcodestr, "$rd, $rs1, $imm6"> {
|
||
|
|
let Constraints = "$rd = $rd_wb";
|
||
|
|
}
|
||
|
|
|
||
|
|
class CVSIMDR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
|
||
|
|
string opcodestr>
|
||
|
|
: CVInstSIMDRR<funct5, F, funct1, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
|
||
|
|
(ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
|
||
|
|
let rs2 = 0b00000;
|
||
|
|
}
|
||
|
|
|
||
|
|
multiclass CVSIMDBinarySigned<bits<5> funct5, bit F, bit funct1, string mnemonic> {
|
||
|
|
def CV_ # NAME # _H : CVSIMDRR<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;
|
||
|
|
def CV_ # NAME # _B : CVSIMDRR<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;
|
||
|
|
def CV_ # NAME # _SC_H : CVSIMDRR<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;
|
||
|
|
def CV_ # NAME # _SC_B : CVSIMDRR<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;
|
||
|
|
def CV_ # NAME # _SCI_H : CVSIMDRI<funct5, F, 0b110, "cv." # mnemonic # ".sci.h">;
|
||
|
|
def CV_ # NAME # _SCI_B : CVSIMDRI<funct5, F, 0b111, "cv." # mnemonic # ".sci.b">;
|
||
|
|
}
|
||
|
|
|
||
|
|
multiclass CVSIMDBinaryUnsigned<bits<5> funct5, bit F, bit funct1, string mnemonic> {
|
||
|
|
def CV_ # NAME # _H : CVSIMDRR<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;
|
||
|
|
def CV_ # NAME # _B : CVSIMDRR<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;
|
||
|
|
def CV_ # NAME # _SC_H : CVSIMDRR<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;
|
||
|
|
def CV_ # NAME # _SC_B : CVSIMDRR<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;
|
||
|
|
def CV_ # NAME # _SCI_H : CVSIMDRU<funct5, F, 0b110, "cv." # mnemonic # ".sci.h">;
|
||
|
|
def CV_ # NAME # _SCI_B : CVSIMDRU<funct5, F, 0b111, "cv." # mnemonic # ".sci.b">;
|
||
|
|
}
|
||
|
|
|
||
|
|
multiclass CVSIMDShift<bits<5> funct5, bit F, bit funct1, string mnemonic> {
|
||
|
|
def CV_ # NAME # _H : CVSIMDRR<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;
|
||
|
|
def CV_ # NAME # _B : CVSIMDRR<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;
|
||
|
|
def CV_ # NAME # _SC_H : CVSIMDRR<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;
|
||
|
|
def CV_ # NAME # _SC_B : CVSIMDRR<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;
|
||
|
|
def CV_ # NAME # _SCI_H : CVSIMDRU<funct5, F, 0b110, "cv." # mnemonic # ".sci.h", uimm4>;
|
||
|
|
def CV_ # NAME # _SCI_B : CVSIMDRU<funct5, F, 0b111, "cv." # mnemonic # ".sci.b", uimm3>;
|
||
|
|
}
|
||
|
|
|
||
|
|
multiclass CVSIMDBinarySignedWb<bits<5> funct5, bit F, bit funct1, string mnemonic> {
|
||
|
|
def CV_ # NAME # _H : CVSIMDRRWb<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;
|
||
|
|
def CV_ # NAME # _B : CVSIMDRRWb<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;
|
||
|
|
def CV_ # NAME # _SC_H : CVSIMDRRWb<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;
|
||
|
|
def CV_ # NAME # _SC_B : CVSIMDRRWb<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;
|
||
|
|
def CV_ # NAME # _SCI_H : CVSIMDRIWb<funct5, F, 0b110, "cv." # mnemonic # ".sci.h">;
|
||
|
|
def CV_ # NAME # _SCI_B : CVSIMDRIWb<funct5, F, 0b111, "cv." # mnemonic # ".sci.b">;
|
||
|
|
}
|
||
|
|
|
||
|
|
multiclass CVSIMDBinaryUnsignedWb<bits<5> funct5, bit F, bit funct1, string mnemonic> {
|
||
|
|
def CV_ # NAME # _H : CVSIMDRRWb<funct5, F, funct1, 0b000, "cv." # mnemonic # ".h">;
|
||
|
|
def CV_ # NAME # _B : CVSIMDRRWb<funct5, F, funct1, 0b001, "cv." # mnemonic # ".b">;
|
||
|
|
def CV_ # NAME # _SC_H : CVSIMDRRWb<funct5, F, funct1, 0b100, "cv." # mnemonic # ".sc.h">;
|
||
|
|
def CV_ # NAME # _SC_B : CVSIMDRRWb<funct5, F, funct1, 0b101, "cv." # mnemonic # ".sc.b">;
|
||
|
|
def CV_ # NAME # _SCI_H : CVSIMDRUWb<funct5, F, 0b110, "cv." # mnemonic # ".sci.h">;
|
||
|
|
def CV_ # NAME # _SCI_B : CVSIMDRUWb<funct5, F, 0b111, "cv." # mnemonic # ".sci.b">;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
let Predicates = [HasVendorXCVsimd, IsRV32],
|
||
|
|
hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
|
||
|
|
defm ADD : CVSIMDBinarySigned<0b00000, 0, 0, "add">;
|
||
|
|
defm SUB : CVSIMDBinarySigned<0b00001, 0, 0, "sub">;
|
||
|
|
defm AVG : CVSIMDBinarySigned<0b00010, 0, 0, "avg">;
|
||
|
|
defm AVGU : CVSIMDBinaryUnsigned<0b00011, 0, 0, "avgu">;
|
||
|
|
defm MIN : CVSIMDBinarySigned<0b00100, 0, 0, "min">;
|
||
|
|
defm MINU : CVSIMDBinaryUnsigned<0b00101, 0, 0, "minu">;
|
||
|
|
defm MAX : CVSIMDBinarySigned<0b00110, 0, 0, "max">;
|
||
|
|
defm MAXU : CVSIMDBinaryUnsigned<0b00111, 0, 0, "maxu">;
|
||
|
|
defm SRL : CVSIMDShift<0b01000, 0, 0, "srl">;
|
||
|
|
defm SRA : CVSIMDShift<0b01001, 0, 0, "sra">;
|
||
|
|
defm SLL : CVSIMDShift<0b01010, 0, 0, "sll">;
|
||
|
|
defm OR : CVSIMDBinarySigned<0b01011, 0, 0, "or">;
|
||
|
|
defm XOR : CVSIMDBinarySigned<0b01100, 0, 0, "xor">;
|
||
|
|
defm AND : CVSIMDBinarySigned<0b01101, 0, 0, "and">;
|
||
|
|
|
||
|
|
def CV_ABS_H : CVSIMDR<0b01110, 0, 0, 0b000, "cv.abs.h">;
|
||
|
|
def CV_ABS_B : CVSIMDR<0b01110, 0, 0, 0b001, "cv.abs.b">;
|
||
|
|
|
||
|
|
// 0b01111xx: UNDEF
|
||
|
|
|
||
|
|
defm DOTUP : CVSIMDBinaryUnsigned<0b10000, 0, 0, "dotup">;
|
||
|
|
defm DOTUSP : CVSIMDBinarySigned<0b10001, 0, 0, "dotusp">;
|
||
|
|
defm DOTSP : CVSIMDBinarySigned<0b10010, 0, 0, "dotsp">;
|
||
|
|
defm SDOTUP : CVSIMDBinaryUnsignedWb<0b10011, 0, 0, "sdotup">;
|
||
|
|
defm SDOTUSP : CVSIMDBinarySignedWb<0b10100, 0, 0, "sdotusp">;
|
||
|
|
defm SDOTSP : CVSIMDBinarySignedWb<0b10101, 0, 0, "sdotsp">;
|
||
|
|
|
||
|
|
// 0b10110xx: UNDEF
|
||
|
|
|
||
|
|
def CV_EXTRACT_H : CVSIMDRU<0b10111, 0, 0b000, "cv.extract.h">;
|
||
|
|
def CV_EXTRACT_B : CVSIMDRU<0b10111, 0, 0b001, "cv.extract.b">;
|
||
|
|
def CV_EXTRACTU_H : CVSIMDRU<0b10111, 0, 0b010, "cv.extractu.h">;
|
||
|
|
def CV_EXTRACTU_B : CVSIMDRU<0b10111, 0, 0b011, "cv.extractu.b">;
|
||
|
|
def CV_INSERT_H : CVSIMDRUWb<0b10111, 0, 0b100, "cv.insert.h">;
|
||
|
|
def CV_INSERT_B : CVSIMDRUWb<0b10111, 0, 0b101, "cv.insert.b">;
|
||
|
|
|
||
|
|
def CV_SHUFFLE_H : CVSIMDRR<0b11000, 0, 0, 0b000, "cv.shuffle.h">;
|
||
|
|
def CV_SHUFFLE_B : CVSIMDRR<0b11000, 0, 0, 0b001, "cv.shuffle.b">;
|
||
|
|
def CV_SHUFFLE_SCI_H : CVSIMDRU<0b11000, 0, 0b110, "cv.shuffle.sci.h">;
|
||
|
|
def CV_SHUFFLEI0_SCI_B : CVSIMDRU<0b11000, 0, 0b111, "cv.shufflei0.sci.b">;
|
||
|
|
|
||
|
|
def CV_SHUFFLEI1_SCI_B : CVSIMDRU<0b11001, 0, 0b111, "cv.shufflei1.sci.b">;
|
||
|
|
|
||
|
|
def CV_SHUFFLEI2_SCI_B : CVSIMDRU<0b11010, 0, 0b111, "cv.shufflei2.sci.b">;
|
||
|
|
|
||
|
|
def CV_SHUFFLEI3_SCI_B : CVSIMDRU<0b11011, 0, 0b111, "cv.shufflei3.sci.b">;
|
||
|
|
|
||
|
|
def CV_SHUFFLE2_H : CVSIMDRRWb<0b11100, 0, 0, 0b000, "cv.shuffle2.h">;
|
||
|
|
def CV_SHUFFLE2_B : CVSIMDRRWb<0b11100, 0, 0, 0b001, "cv.shuffle2.b">;
|
||
|
|
|
||
|
|
// 0b11101xx: UNDEF
|
||
|
|
|
||
|
|
def CV_PACK : CVSIMDRR<0b11110, 0, 0, 0b000, "cv.pack">;
|
||
|
|
def CV_PACK_H : CVSIMDRR<0b11110, 0, 1, 0b000, "cv.pack.h">;
|
||
|
|
|
||
|
|
def CV_PACKHI_B : CVSIMDRRWb<0b11111, 0, 1, 0b001, "cv.packhi.b">;
|
||
|
|
def CV_PACKLO_B : CVSIMDRRWb<0b11111, 0, 0, 0b001, "cv.packlo.b">;
|
||
|
|
|
||
|
|
defm CMPEQ : CVSIMDBinarySigned<0b00000, 1, 0, "cmpeq">;
|
||
|
|
defm CMPNE : CVSIMDBinarySigned<0b00001, 1, 0, "cmpne">;
|
||
|
|
defm CMPGT : CVSIMDBinarySigned<0b00010, 1, 0, "cmpgt">;
|
||
|
|
defm CMPGE : CVSIMDBinarySigned<0b00011, 1, 0, "cmpge">;
|
||
|
|
defm CMPLT : CVSIMDBinarySigned<0b00100, 1, 0, "cmplt">;
|
||
|
|
defm CMPLE : CVSIMDBinarySigned<0b00101, 1, 0, "cmple">;
|
||
|
|
defm CMPGTU : CVSIMDBinaryUnsigned<0b00110, 1, 0, "cmpgtu">;
|
||
|
|
defm CMPGEU : CVSIMDBinaryUnsigned<0b00111, 1, 0, "cmpgeu">;
|
||
|
|
defm CMPLTU : CVSIMDBinaryUnsigned<0b01000, 1, 0, "cmpltu">;
|
||
|
|
defm CMPLEU : CVSIMDBinaryUnsigned<0b01001, 1, 0, "cmpleu">;
|
||
|
|
|
||
|
|
def CV_CPLXMUL_R : CVSIMDRRWb<0b01010, 1, 0, 0b000, "cv.cplxmul.r">;
|
||
|
|
def CV_CPLXMUL_I : CVSIMDRRWb<0b01010, 1, 1, 0b000, "cv.cplxmul.i">;
|
||
|
|
def CV_CPLXMUL_R_DIV2 : CVSIMDRRWb<0b01010, 1, 0, 0b010, "cv.cplxmul.r.div2">;
|
||
|
|
def CV_CPLXMUL_I_DIV2 : CVSIMDRRWb<0b01010, 1, 1, 0b010, "cv.cplxmul.i.div2">;
|
||
|
|
def CV_CPLXMUL_R_DIV4 : CVSIMDRRWb<0b01010, 1, 0, 0b100, "cv.cplxmul.r.div4">;
|
||
|
|
def CV_CPLXMUL_I_DIV4 : CVSIMDRRWb<0b01010, 1, 1, 0b100, "cv.cplxmul.i.div4">;
|
||
|
|
def CV_CPLXMUL_R_DIV8 : CVSIMDRRWb<0b01010, 1, 0, 0b110, "cv.cplxmul.r.div8">;
|
||
|
|
def CV_CPLXMUL_I_DIV8 : CVSIMDRRWb<0b01010, 1, 1, 0b110, "cv.cplxmul.i.div8">;
|
||
|
|
|
||
|
|
def CV_CPLXCONJ : CVSIMDR<0b01011, 1, 0, 0b000, "cv.cplxconj">;
|
||
|
|
|
||
|
|
// 0b01011xx: UNDEF
|
||
|
|
|
||
|
|
def CV_SUBROTMJ : CVSIMDRR<0b01100, 1, 0, 0b000, "cv.subrotmj">;
|
||
|
|
def CV_SUBROTMJ_DIV2 : CVSIMDRR<0b01100, 1, 0, 0b010, "cv.subrotmj.div2">;
|
||
|
|
def CV_SUBROTMJ_DIV4 : CVSIMDRR<0b01100, 1, 0, 0b100, "cv.subrotmj.div4">;
|
||
|
|
def CV_SUBROTMJ_DIV8 : CVSIMDRR<0b01100, 1, 0, 0b110, "cv.subrotmj.div8">;
|
||
|
|
|
||
|
|
def CV_ADD_DIV2 : CVSIMDRR<0b01101, 1, 0, 0b010, "cv.add.div2">;
|
||
|
|
def CV_ADD_DIV4 : CVSIMDRR<0b01101, 1, 0, 0b100, "cv.add.div4">;
|
||
|
|
def CV_ADD_DIV8 : CVSIMDRR<0b01101, 1, 0, 0b110, "cv.add.div8">;
|
||
|
|
|
||
|
|
def CV_SUB_DIV2 : CVSIMDRR<0b01110, 1, 0, 0b010, "cv.sub.div2">;
|
||
|
|
def CV_SUB_DIV4 : CVSIMDRR<0b01110, 1, 0, 0b100, "cv.sub.div4">;
|
||
|
|
def CV_SUB_DIV8 : CVSIMDRR<0b01110, 1, 0, 0b110, "cv.sub.div8">;
|
||
|
|
}
|
||
|
|
|
||
|
|
class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,
|
||
|
|
string opcodestr, string argstr>
|
||
|
|
: RVInstB<funct3, OPC_CUSTOM_0, outs, ins, opcodestr, argstr> {
|
||
|
|
bits<5> imm5;
|
||
|
|
let rs2 = imm5;
|
||
|
|
let DecoderNamespace = "XCVbi";
|
||
|
|
}
|
||
|
|
|
||
|
|
let Predicates = [HasVendorXCVbi, IsRV32], hasSideEffects = 0, mayLoad = 0,
|
||
|
|
mayStore = 0, isBranch = 1, isTerminator = 1 in {
|
||
|
|
// Immediate branching operations
|
||
|
|
def CV_BEQIMM : CVInstImmBranch<0b110, (outs),
|
||
|
|
(ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
|
||
|
|
"cv.beqimm", "$rs1, $imm5, $imm12">, Sched<[]>;
|
||
|
|
def CV_BNEIMM : CVInstImmBranch<0b111, (outs),
|
||
|
|
(ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
|
||
|
|
"cv.bneimm", "$rs1, $imm5, $imm12">, Sched<[]>;
|
||
|
|
}
|
||
|
|
|
||
|
|
def CVrrAsmOperand : AsmOperandClass {
|
||
|
|
let Name = "RegReg";
|
||
|
|
let ParserMethod = "parseRegReg";
|
||
|
|
let DiagnosticType = "InvalidRegReg";
|
||
|
|
}
|
||
|
|
|
||
|
|
def CVrr : Operand<OtherVT> {
|
||
|
|
let ParserMatchClass = CVrrAsmOperand;
|
||
|
|
let EncoderMethod = "getRegReg";
|
||
|
|
let DecoderMethod = "decodeRegReg";
|
||
|
|
let PrintMethod = "printRegReg";
|
||
|
|
}
|
||
|
|
|
||
|
|
class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
|
||
|
|
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, simm12:$imm12),
|
||
|
|
opcodestr, "$rd, (${rs1}), ${imm12}"> {
|
||
|
|
let Constraints = "$rs1_wb = $rs1";
|
||
|
|
let DecoderNamespace = "XCVmem";
|
||
|
|
}
|
||
|
|
|
||
|
|
class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
|
||
|
|
: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd, GPR:$rs1_wb), (ins GPRMem:$rs1, GPR:$rs2),
|
||
|
|
opcodestr, "$rd, (${rs1}), ${rs2}"> {
|
||
|
|
let Constraints = "$rs1_wb = $rs1";
|
||
|
|
let DecoderNamespace = "XCVmem";
|
||
|
|
}
|
||
|
|
|
||
|
|
class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
|
||
|
|
: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins CVrr:$cvrr),
|
||
|
|
opcodestr, "$rd, $cvrr"> {
|
||
|
|
bits<5> rd;
|
||
|
|
bits<10> cvrr;
|
||
|
|
|
||
|
|
let Inst{31-25} = funct7;
|
||
|
|
let Inst{24-20} = cvrr{4-0};
|
||
|
|
let Inst{19-15} = cvrr{9-5};
|
||
|
|
let Inst{14-12} = funct3;
|
||
|
|
let Inst{11-7} = rd;
|
||
|
|
let DecoderNamespace = "XCVmem";
|
||
|
|
}
|
||
|
|
|
||
|
|
let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
|
||
|
|
mayLoad = 1, mayStore = 0, Constraints = "$rs1_wb = $rs1" in {
|
||
|
|
// Register-Immediate load with post-increment
|
||
|
|
def CV_LB_ri_inc : CVLoad_ri_inc<0b000, "cv.lb">;
|
||
|
|
def CV_LBU_ri_inc : CVLoad_ri_inc<0b100, "cv.lbu">;
|
||
|
|
def CV_LH_ri_inc : CVLoad_ri_inc<0b001, "cv.lh">;
|
||
|
|
def CV_LHU_ri_inc : CVLoad_ri_inc<0b101, "cv.lhu">;
|
||
|
|
def CV_LW_ri_inc : CVLoad_ri_inc<0b010, "cv.lw">;
|
||
|
|
|
||
|
|
// Register-Register load with post-increment
|
||
|
|
def CV_LB_rr_inc : CVLoad_rr_inc<0b0000000, 0b011, "cv.lb">;
|
||
|
|
def CV_LBU_rr_inc : CVLoad_rr_inc<0b0001000, 0b011, "cv.lbu">;
|
||
|
|
def CV_LH_rr_inc : CVLoad_rr_inc<0b0000001, 0b011, "cv.lh">;
|
||
|
|
def CV_LHU_rr_inc : CVLoad_rr_inc<0b0001001, 0b011, "cv.lhu">;
|
||
|
|
def CV_LW_rr_inc : CVLoad_rr_inc<0b0000010, 0b011, "cv.lw">;
|
||
|
|
}
|
||
|
|
|
||
|
|
let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
|
||
|
|
mayLoad = 1, mayStore = 0 in {
|
||
|
|
// Register-Register load
|
||
|
|
def CV_LB_rr : CVLoad_rr<0b0000100, 0b011, "cv.lb">;
|
||
|
|
def CV_LBU_rr : CVLoad_rr<0b0001100, 0b011, "cv.lbu">;
|
||
|
|
def CV_LH_rr : CVLoad_rr<0b0000101, 0b011, "cv.lh">;
|
||
|
|
def CV_LHU_rr : CVLoad_rr<0b0001101, 0b011, "cv.lhu">;
|
||
|
|
def CV_LW_rr : CVLoad_rr<0b0000110, 0b011, "cv.lw">;
|
||
|
|
}
|
||
|
|
|
||
|
|
class CVStore_ri_inc<bits<3> funct3, string opcodestr>
|
||
|
|
: RVInstS<funct3, OPC_CUSTOM_1, (outs GPR:$rs1_wb),
|
||
|
|
(ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
|
||
|
|
opcodestr, "$rs2, (${rs1}), ${imm12}"> {
|
||
|
|
let Constraints = "$rs1_wb = $rs1";
|
||
|
|
let DecoderNamespace = "XCVmem";
|
||
|
|
}
|
||
|
|
|
||
|
|
class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
|
||
|
|
string opcodestr, string argstr>
|
||
|
|
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
|
||
|
|
bits<5> rs3;
|
||
|
|
bits<5> rs2;
|
||
|
|
bits<5> rs1;
|
||
|
|
|
||
|
|
let Inst{31-25} = funct7;
|
||
|
|
let Inst{24-20} = rs2;
|
||
|
|
let Inst{19-15} = rs1;
|
||
|
|
let Inst{14-12} = funct3;
|
||
|
|
let Inst{11-7} = rs3;
|
||
|
|
let Inst{6-0} = OPC_CUSTOM_1.Value;
|
||
|
|
let DecoderNamespace = "XCVmem";
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
class CVStore_rr<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
|
||
|
|
string opcodestr, string argstr>
|
||
|
|
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
|
||
|
|
bits<5> rs2;
|
||
|
|
bits<10> cvrr;
|
||
|
|
|
||
|
|
let Inst{31-25} = funct7;
|
||
|
|
let Inst{24-20} = rs2;
|
||
|
|
let Inst{19-15} = cvrr{9-5};
|
||
|
|
let Inst{14-12} = funct3;
|
||
|
|
let Inst{11-7} = cvrr{4-0};
|
||
|
|
let Inst{6-0} = OPC_CUSTOM_1.Value;
|
||
|
|
let DecoderNamespace = "XCVmem";
|
||
|
|
}
|
||
|
|
|
||
|
|
let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
|
||
|
|
mayLoad = 0, mayStore = 1, Constraints = "$rs1_wb = $rs1" in {
|
||
|
|
// Register-Immediate store with post-increment
|
||
|
|
def CV_SB_ri_inc : CVStore_ri_inc<0b000, "cv.sb">;
|
||
|
|
def CV_SH_ri_inc : CVStore_ri_inc<0b001, "cv.sh">;
|
||
|
|
def CV_SW_ri_inc : CVStore_ri_inc<0b010, "cv.sw">;
|
||
|
|
|
||
|
|
// Register-Register store with post-increment
|
||
|
|
def CV_SB_rr_inc : CVStore_rr_inc<0b011, 0b0010000,
|
||
|
|
(outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
|
||
|
|
"cv.sb", "$rs2, (${rs1}), ${rs3}">;
|
||
|
|
def CV_SH_rr_inc : CVStore_rr_inc<0b011, 0b0010001,
|
||
|
|
(outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
|
||
|
|
"cv.sh", "$rs2, (${rs1}), ${rs3}">;
|
||
|
|
def CV_SW_rr_inc : CVStore_rr_inc<0b011, 0b0010010,
|
||
|
|
(outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
|
||
|
|
"cv.sw", "$rs2, (${rs1}), ${rs3}">;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
let Predicates = [HasVendorXCVmem, IsRV32], hasSideEffects = 0,
|
||
|
|
mayLoad = 0, mayStore = 1 in {
|
||
|
|
// Register-Register store
|
||
|
|
def CV_SB_rr : CVStore_rr<0b011, 0b0010100,
|
||
|
|
(outs), (ins GPR:$rs2, CVrr:$cvrr),
|
||
|
|
"cv.sb", "$rs2, $cvrr">;
|
||
|
|
def CV_SH_rr : CVStore_rr<0b011, 0b0010101,
|
||
|
|
(outs), (ins GPR:$rs2, CVrr:$cvrr),
|
||
|
|
"cv.sh", "$rs2, $cvrr">;
|
||
|
|
def CV_SW_rr : CVStore_rr<0b011, 0b0010110,
|
||
|
|
(outs), (ins GPR:$rs2, CVrr:$cvrr),
|
||
|
|
"cv.sw", "$rs2, $cvrr">;
|
||
|
|
}
|
||
|
|
|
||
|
|
let DecoderNamespace = "XCVelw" in
|
||
|
|
class CVLoad_ri<bits<3> funct3, string opcodestr>
|
||
|
|
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
|
||
|
|
(ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
|
||
|
|
|
||
|
|
let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 0,
|
||
|
|
mayLoad = 1, mayStore = 0 in {
|
||
|
|
// Event load
|
||
|
|
def CV_ELW : CVLoad_ri<0b011, "cv.elw">;
|
||
|
|
}
|
||
|
|
|
||
|
|
def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
|
||
|
|
def cv_tuimm5 : TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
|
||
|
|
def cv_uimm10 : ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;
|
||
|
|
|
||
|
|
def CV_LO5: SDNodeXForm<imm, [{
|
||
|
|
return CurDAG->getTargetConstant(N->getZExtValue() & 0x1f, SDLoc(N),
|
||
|
|
N->getValueType(0));
|
||
|
|
}]>;
|
||
|
|
|
||
|
|
def CV_HI5: SDNodeXForm<imm, [{
|
||
|
|
return CurDAG->getTargetConstant(N->getZExtValue() >> 5, SDLoc(N),
|
||
|
|
N->getValueType(0));
|
||
|
|
}]>;
|
||
|
|
|
||
|
|
multiclass PatCoreVBitManip<Intrinsic intr> {
|
||
|
|
def : PatGprGpr<intr, !cast<RVInst>("CV_" # NAME # "R")>;
|
||
|
|
def : Pat<(intr GPR:$rs1, cv_uimm10:$imm),
|
||
|
|
(!cast<RVInst>("CV_" # NAME)
|
||
|
|
GPR:$rs1, (CV_HI5 cv_uimm10:$imm), (CV_LO5 cv_uimm10:$imm))>;
|
||
|
|
}
|
||
|
|
|
||
|
|
let Predicates = [HasVendorXCVbitmanip, IsRV32] in {
|
||
|
|
defm EXTRACT : PatCoreVBitManip<int_riscv_cv_bitmanip_extract>;
|
||
|
|
defm EXTRACTU : PatCoreVBitManip<int_riscv_cv_bitmanip_extractu>;
|
||
|
|
defm BCLR : PatCoreVBitManip<int_riscv_cv_bitmanip_bclr>;
|
||
|
|
defm BSET : PatCoreVBitManip<int_riscv_cv_bitmanip_bset>;
|
||
|
|
|
||
|
|
def : Pat<(int_riscv_cv_bitmanip_insert GPR:$rs1, GPR:$rs2, GPR:$rd),
|
||
|
|
(CV_INSERTR GPR:$rd, GPR:$rs1, GPR:$rs2)>;
|
||
|
|
def : Pat<(int_riscv_cv_bitmanip_insert GPR:$rs1, cv_uimm10:$imm, GPR:$rd),
|
||
|
|
(CV_INSERT GPR:$rd, GPR:$rs1, (CV_HI5 cv_uimm10:$imm),
|
||
|
|
(CV_LO5 cv_uimm10:$imm))>;
|
||
|
|
|
||
|
|
def : PatGpr<cttz, CV_FF1>;
|
||
|
|
def : PatGpr<ctlz, CV_FL1>;
|
||
|
|
def : PatGpr<int_riscv_cv_bitmanip_clb, CV_CLB>;
|
||
|
|
def : PatGpr<ctpop, CV_CNT>;
|
||
|
|
|
||
|
|
def : PatGprGpr<rotr, CV_ROR>;
|
||
|
|
|
||
|
|
def : Pat<(int_riscv_cv_bitmanip_bitrev GPR:$rs1, cv_tuimm5:$pts,
|
||
|
|
cv_tuimm2:$radix),
|
||
|
|
(CV_BITREV GPR:$rs1, cv_tuimm2:$radix, cv_tuimm5:$pts)>;
|
||
|
|
def : Pat<(bitreverse (XLenVT GPR:$rs)), (CV_BITREV GPR:$rs, 0, 0)>;
|
||
|
|
}
|