263 lines
11 KiB
TableGen
263 lines
11 KiB
TableGen
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//===-- RISCVInstrInfoZfa.td - RISC-V 'Zfa' instructions ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'Zfa'
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// additional floating-point extension, version 1.0.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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// 5-bit floating-point immediate encodings.
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def LoadFPImmOperand : AsmOperandClass {
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let Name = "LoadFPImm";
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let ParserMethod = "parseFPImm";
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let RenderMethod = "addFPImmOperands";
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let DiagnosticType = "InvalidLoadFPImm";
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}
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def loadfpimm : Operand<XLenVT> {
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let ParserMatchClass = LoadFPImmOperand;
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let PrintMethod = "printFPImmOperand";
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}
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def RTZArg : AsmOperandClass {
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let Name = "RTZArg";
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let RenderMethod = "addFRMArgOperands";
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let DiagnosticType = "InvalidRTZArg";
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let ParserMethod = "parseFRMArg";
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}
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def rtzarg : Operand<XLenVT> {
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let ParserMatchClass = RTZArg;
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let PrintMethod = "printFRMArg";
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let DecoderMethod = "decodeFRMArg";
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}
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
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class FPBinaryOp_rr<bits<7> funct7, bits<3> funct3, DAGOperand rdty,
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DAGOperand rsty, string opcodestr>
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: RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd),
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(ins rsty:$rs1, rsty:$rs2), opcodestr, "$rd, $rs1, $rs2">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPFLI_r<bits<7> funct7, bits<5> rs2val, bits<3> funct3,
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DAGOperand rdty, string opcodestr>
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: RVInstR<funct7, funct3, OPC_OP_FP, (outs rdty:$rd),
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(ins loadfpimm:$imm), opcodestr, "$rd, $imm"> {
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bits<5> imm;
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let rs2 = rs2val;
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let rs1 = imm;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
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UseNamedOperandTable = 1, hasPostISelHook = 1 in
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class FPUnaryOp_r_rtz<bits<7> funct7, bits<5> rs2val, DAGOperand rdty,
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DAGOperand rs1ty, string opcodestr>
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: RVInstRFrm<funct7, OPC_OP_FP, (outs rdty:$rd),
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(ins rs1ty:$rs1, rtzarg:$frm), opcodestr,
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"$rd, $rs1$frm"> {
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let rs2 = rs2val;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZfa] in {
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in
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def FLI_S : FPFLI_r<0b1111000, 0b00001, 0b000, FPR32, "fli.s">,
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Sched<[WriteFLI32]>;
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let SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in {
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def FMINM_S: FPALU_rr<0b0010100, 0b010, "fminm.s", FPR32, Commutable=1>;
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def FMAXM_S: FPALU_rr<0b0010100, 0b011, "fmaxm.s", FPR32, Commutable=1>;
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}
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def FROUND_S : FPUnaryOp_r_frm<0b0100000, 0b00100, FPR32, FPR32, "fround.s">,
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Sched<[WriteFRoundF32, ReadFRoundF32]>;
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def FROUNDNX_S : FPUnaryOp_r_frm<0b0100000, 0b00101, FPR32, FPR32, "froundnx.s">,
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Sched<[WriteFRoundF32, ReadFRoundF32]>;
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let SchedRW = [WriteFCmp32, ReadFCmp32, ReadFCmp32] in {
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def FLTQ_S : FPCmp_rr<0b1010000, 0b101, "fltq.s", FPR32>;
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def FLEQ_S : FPCmp_rr<0b1010000, 0b100, "fleq.s", FPR32>;
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}
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} // Predicates = [HasStdExtZfa]
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let Predicates = [HasStdExtZfa, HasStdExtD] in {
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in
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def FLI_D : FPFLI_r<0b1111001, 0b00001, 0b000, FPR64, "fli.d">,
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Sched<[WriteFLI64]>;
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let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in {
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def FMINM_D: FPALU_rr<0b0010101, 0b010, "fminm.d", FPR64, Commutable=1>;
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def FMAXM_D: FPALU_rr<0b0010101, 0b011, "fmaxm.d", FPR64, Commutable=1>;
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}
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def FROUND_D : FPUnaryOp_r_frm<0b0100001, 0b00100, FPR64, FPR64, "fround.d">,
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Sched<[WriteFRoundF64, ReadFRoundF64]>;
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def FROUNDNX_D : FPUnaryOp_r_frm<0b0100001, 0b00101, FPR64, FPR64, "froundnx.d">,
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Sched<[WriteFRoundF64, ReadFRoundF64]>;
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let IsSignExtendingOpW = 1 in
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def FCVTMOD_W_D
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: FPUnaryOp_r_rtz<0b1100001, 0b01000, GPR, FPR64, "fcvtmod.w.d">,
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Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
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let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in {
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def FLTQ_D : FPCmp_rr<0b1010001, 0b101, "fltq.d", FPR64>;
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def FLEQ_D : FPCmp_rr<0b1010001, 0b100, "fleq.d", FPR64>;
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}
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} // Predicates = [HasStdExtZfa, HasStdExtD]
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let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
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let mayRaiseFPException = 0 in {
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def FMVH_X_D : FPUnaryOp_r<0b1110001, 0b00001, 0b000, GPR, FPR64, "fmvh.x.d">,
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Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;
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def FMVP_D_X : FPBinaryOp_rr<0b1011001, 0b000, FPR64, GPR, "fmvp.d.x">,
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Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>;
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}
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let isCodeGenOnly = 1, mayRaiseFPException = 0 in
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def FMV_X_W_FPR64 : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR64,
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"fmv.x.w">,
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Sched<[WriteFMovF64ToI64, ReadFMovF64ToI64]>;
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} // Predicates = [HasStdExtZfa, HasStdExtD, IsRV32]
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let Predicates = [HasStdExtZfa, HasStdExtZfhOrZvfh] in
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let isReMaterializable = 1, isAsCheapAsAMove = 1 in
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def FLI_H : FPFLI_r<0b1111010, 0b00001, 0b000, FPR16, "fli.h">,
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Sched<[WriteFLI16]>;
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let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
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let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in {
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def FMINM_H: FPALU_rr<0b0010110, 0b010, "fminm.h", FPR16, Commutable=1>;
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def FMAXM_H: FPALU_rr<0b0010110, 0b011, "fmaxm.h", FPR16, Commutable=1>;
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}
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def FROUND_H : FPUnaryOp_r_frm<0b0100010, 0b00100, FPR16, FPR16, "fround.h">,
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Sched<[WriteFRoundF16, ReadFRoundF16]>;
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def FROUNDNX_H : FPUnaryOp_r_frm<0b0100010, 0b00101, FPR16, FPR16, "froundnx.h">,
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Sched<[WriteFRoundF16, ReadFRoundF16]>;
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let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in {
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def FLTQ_H : FPCmp_rr<0b1010010, 0b101, "fltq.h", FPR16>;
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def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
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}
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} // Predicates = [HasStdExtZfa, HasStdExtZfh]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZfa] in {
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def : InstAlias<"fgtq.s $rd, $rs, $rt",
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(FLTQ_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
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def : InstAlias<"fgeq.s $rd, $rs, $rt",
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(FLEQ_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;
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}
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let Predicates = [HasStdExtZfa, HasStdExtD] in {
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def : InstAlias<"fgtq.d $rd, $rs, $rt",
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(FLTQ_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
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def : InstAlias<"fgeq.d $rd, $rs, $rt",
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(FLEQ_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
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}
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let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
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def : InstAlias<"fgtq.h $rd, $rs, $rt",
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(FLTQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
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def : InstAlias<"fgeq.h $rd, $rs, $rt",
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(FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
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}
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//===----------------------------------------------------------------------===//
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// Codegen patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZfa] in {
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def: PatFprFpr<fminimum, FMINM_S, FPR32, f32>;
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def: PatFprFpr<fmaximum, FMAXM_S, FPR32, f32>;
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// frint rounds according to the current rounding mode and detects
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// inexact conditions.
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def: Pat<(any_frint FPR32:$rs1), (FROUNDNX_S FPR32:$rs1, FRM_DYN)>;
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// fnearbyint is like frint but does not detect inexact conditions.
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def: Pat<(any_fnearbyint FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_DYN)>;
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def: Pat<(any_fround FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RMM)>;
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def: Pat<(any_ffloor FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RDN)>;
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def: Pat<(any_fceil FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RUP)>;
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def: Pat<(any_ftrunc FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RTZ)>;
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def: PatSetCC<FPR32, strict_fsetcc, SETLT, FLTQ_S, f32>;
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def: PatSetCC<FPR32, strict_fsetcc, SETOLT, FLTQ_S, f32>;
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def: PatSetCC<FPR32, strict_fsetcc, SETLE, FLEQ_S, f32>;
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def: PatSetCC<FPR32, strict_fsetcc, SETOLE, FLEQ_S, f32>;
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} // Predicates = [HasStdExtZfa]
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let Predicates = [HasStdExtZfa, HasStdExtD] in {
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def: PatFprFpr<fminimum, FMINM_D, FPR64, f64>;
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def: PatFprFpr<fmaximum, FMAXM_D, FPR64, f64>;
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// frint rounds according to the current rounding mode and detects
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// inexact conditions.
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def: Pat<(any_frint FPR64:$rs1), (FROUNDNX_D FPR64:$rs1, FRM_DYN)>;
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// fnearbyint is like frint but does not detect inexact conditions.
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def: Pat<(any_fnearbyint FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_DYN)>;
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def: Pat<(any_fround FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RMM)>;
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def: Pat<(any_froundeven FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RNE)>;
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def: Pat<(any_ffloor FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RDN)>;
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def: Pat<(any_fceil FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RUP)>;
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def: Pat<(any_ftrunc FPR64:$rs1), (FROUND_D FPR64:$rs1, FRM_RTZ)>;
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def: PatSetCC<FPR64, strict_fsetcc, SETLT, FLTQ_D, f64>;
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def: PatSetCC<FPR64, strict_fsetcc, SETOLT, FLTQ_D, f64>;
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def: PatSetCC<FPR64, strict_fsetcc, SETLE, FLEQ_D, f64>;
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def: PatSetCC<FPR64, strict_fsetcc, SETOLE, FLEQ_D, f64>;
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} // Predicates = [HasStdExtZfa, HasStdExtD]
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let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
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def : Pat<(RISCVBuildPairF64 GPR:$rs1, GPR:$rs2),
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(FMVP_D_X GPR:$rs1, GPR:$rs2)>;
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}
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let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
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def: PatFprFpr<fminimum, FMINM_H, FPR16, f16>;
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def: PatFprFpr<fmaximum, FMAXM_H, FPR16, f16>;
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// frint rounds according to the current rounding mode and detects
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// inexact conditions.
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def: Pat<(f16 (any_frint FPR16:$rs1)), (FROUNDNX_H FPR16:$rs1, FRM_DYN)>;
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// fnearbyint is like frint but does not detect inexact conditions.
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def: Pat<(f16 (any_fnearbyint FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_DYN)>;
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def: Pat<(f16 (any_fround FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RMM)>;
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def: Pat<(f16 (any_froundeven FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RNE)>;
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def: Pat<(f16 (any_ffloor FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RDN)>;
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def: Pat<(f16 (any_fceil FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RUP)>;
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def: Pat<(f16 (any_ftrunc FPR16:$rs1)), (FROUND_H FPR16:$rs1, FRM_RTZ)>;
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def: PatSetCC<FPR16, strict_fsetcc, SETLT, FLTQ_H, f16>;
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def: PatSetCC<FPR16, strict_fsetcc, SETOLT, FLTQ_H, f16>;
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def: PatSetCC<FPR16, strict_fsetcc, SETLE, FLEQ_H, f16>;
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def: PatSetCC<FPR16, strict_fsetcc, SETOLE, FLEQ_H, f16>;
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} // Predicates = [HasStdExtZfa, HasStdExtZfh]
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