351 lines
17 KiB
TableGen
351 lines
17 KiB
TableGen
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//===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V processors supported.
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//===----------------------------------------------------------------------===//
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class RISCVTuneInfo {
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bits<8> PrefFunctionAlignment = 1;
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bits<8> PrefLoopAlignment = 1;
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// Information needed by LoopDataPrefetch.
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bits<16> CacheLineSize = 0;
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bits<16> PrefetchDistance = 0;
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bits<16> MinPrefetchStride = 1;
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bits<32> MaxPrefetchIterationsAhead = -1;
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bits<32> MinimumJumpTableEntries = 5;
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}
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def RISCVTuneInfoTable : GenericTable {
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let FilterClass = "RISCVTuneInfo";
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let CppTypeName = "RISCVTuneInfo";
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let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment",
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"CacheLineSize", "PrefetchDistance",
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"MinPrefetchStride", "MaxPrefetchIterationsAhead",
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"MinimumJumpTableEntries"];
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}
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def getRISCVTuneInfo : SearchIndex {
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let Table = RISCVTuneInfoTable;
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let Key = ["Name"];
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}
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class GenericTuneInfo: RISCVTuneInfo;
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class RISCVProcessorModel<string n,
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SchedMachineModel m,
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list<SubtargetFeature> f,
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list<SubtargetFeature> tunef = [],
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string default_march = "">
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: ProcessorModel<n, m, f, tunef> {
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string DefaultMarch = default_march;
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}
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class RISCVTuneProcessorModel<string n,
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SchedMachineModel m,
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list<SubtargetFeature> tunef = [],
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list<SubtargetFeature> f = []>
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: ProcessorModel<n, m, f,tunef>;
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def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
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NoSchedModel,
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[Feature32Bit]>,
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GenericTuneInfo;
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def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
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NoSchedModel,
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[Feature64Bit]>,
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GenericTuneInfo;
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// Support generic for compatibility with other targets. The triple will be used
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// to change to the appropriate rv32/rv64 version.
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def : ProcessorModel<"generic", NoSchedModel, []>, GenericTuneInfo;
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def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr]>;
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def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr]>;
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def ROCKET : RISCVTuneProcessorModel<"rocket",
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RocketModel>;
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def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
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SiFive7Model,
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[TuneSiFive7]>;
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def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtC]>;
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def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC]>;
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def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC]>;
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def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
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SiFive7Model,
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[Feature32Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC],
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[TuneSiFive7]>;
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def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC]>;
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def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
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SiFive7Model,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZihintpause],
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[TuneSiFive7]>;
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def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC]>;
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def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
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SiFive7Model,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC],
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[TuneSiFive7]>;
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def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtV,
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FeatureStdExtZvl512b,
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FeatureStdExtZfh,
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FeatureStdExtZvfh,
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FeatureStdExtZba,
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FeatureStdExtZbb],
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[TuneSiFive7,
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TuneDLenFactor2]>;
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def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZa64rs,
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FeatureStdExtZic64b,
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FeatureStdExtZicbop,
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FeatureStdExtZicbom,
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FeatureStdExtZicboz,
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FeatureStdExtZiccamoa,
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FeatureStdExtZiccif,
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FeatureStdExtZicclsm,
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FeatureStdExtZiccrse,
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FeatureStdExtZihintntl,
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FeatureStdExtZihintpause,
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FeatureStdExtZihpm,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZfhmin,
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FeatureFastUnalignedAccess],
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[TuneNoDefaultUnroll,
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TuneConditionalCompressedMoveFusion,
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TuneLUIADDIFusion,
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TuneAUIPCADDIFusion]>;
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def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZa64rs,
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FeatureStdExtZic64b,
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FeatureStdExtZicbop,
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FeatureStdExtZicbom,
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FeatureStdExtZicboz,
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FeatureStdExtZiccamoa,
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FeatureStdExtZiccif,
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FeatureStdExtZicclsm,
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FeatureStdExtZiccrse,
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FeatureStdExtZihintntl,
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FeatureStdExtZihintpause,
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FeatureStdExtZihpm,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZfhmin,
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FeatureStdExtV,
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FeatureStdExtZvl128b,
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FeatureStdExtZvbb,
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FeatureStdExtZvknc,
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FeatureStdExtZvkng,
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FeatureStdExtZvksc,
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FeatureStdExtZvksg,
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FeatureFastUnalignedAccess],
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[TuneNoDefaultUnroll,
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TuneConditionalCompressedMoveFusion,
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TuneLUIADDIFusion,
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TuneAUIPCADDIFusion]>;
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def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
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SyntacoreSCR1Model,
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[Feature32Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtC],
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[TuneNoDefaultUnroll]>;
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def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
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SyntacoreSCR1Model,
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[Feature32Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtC],
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[TuneNoDefaultUnroll]>;
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def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr,
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FeatureStdExtZicntr,
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FeatureStdExtZihpm,
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FeatureStdExtZihintpause,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbc,
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FeatureStdExtZbs,
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FeatureStdExtZicbom,
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FeatureStdExtZicbop,
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FeatureStdExtZicboz,
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FeatureVendorXVentanaCondOps],
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[TuneVentanaVeyron,
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TuneLUIADDIFusion,
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TuneAUIPCADDIFusion,
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TuneZExtHFusion,
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TuneZExtWFusion,
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TuneShiftedZExtWFusion,
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TuneLDADDFusion]>;
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def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbc,
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FeatureStdExtZbs,
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FeatureStdExtZkn,
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FeatureStdExtZksed,
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FeatureStdExtZksh,
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FeatureStdExtSvinval,
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FeatureStdExtZicbom,
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FeatureStdExtZicboz]>;
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