183 lines
6.5 KiB
LLVM
183 lines
6.5 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECK,RV32IZFBFMIN %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECK,RV64IZFBFMIN %s
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define bfloat @flh(ptr %a) nounwind {
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; CHECK-LABEL: flh:
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; CHECK: # %bb.0:
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; CHECK-NEXT: flh fa5, 6(a0)
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; CHECK-NEXT: flh fa4, 0(a0)
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa5
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; CHECK-NEXT: fcvt.s.bf16 fa4, fa4
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; CHECK-NEXT: fadd.s fa5, fa4, fa5
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%1 = load bfloat, ptr %a
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%2 = getelementptr bfloat, ptr %a, i32 3
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%3 = load bfloat, ptr %2
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; Use both loaded values in an FP op to ensure an flh is used, even for the
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; soft bfloat ABI
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%4 = fadd bfloat %1, %3
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ret bfloat %4
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}
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define dso_local void @fsh(ptr %a, bfloat %b, bfloat %c) nounwind {
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; CHECK-LABEL: fsh:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
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; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
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; CHECK-NEXT: fadd.s fa5, fa4, fa5
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; CHECK-NEXT: fcvt.bf16.s fa5, fa5
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; CHECK-NEXT: fsh fa5, 0(a0)
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; CHECK-NEXT: fsh fa5, 16(a0)
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; CHECK-NEXT: ret
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%1 = fadd bfloat %b, %c
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store bfloat %1, ptr %a
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%2 = getelementptr bfloat, ptr %a, i32 8
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store bfloat %1, ptr %2
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ret void
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}
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; Check load and store to a global
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@G = dso_local global bfloat 0.0
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define bfloat @flh_fsh_global(bfloat %a, bfloat %b) nounwind {
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; Use %a and %b in an FP op to ensure bfloat precision floating point registers
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; are used, even for the soft bfloat ABI
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; CHECK-LABEL: flh_fsh_global:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
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; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
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; CHECK-NEXT: fadd.s fa5, fa4, fa5
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: lui a0, %hi(G)
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; CHECK-NEXT: flh fa5, %lo(G)(a0)
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; CHECK-NEXT: addi a1, a0, %lo(G)
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; CHECK-NEXT: fsh fa0, %lo(G)(a0)
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; CHECK-NEXT: flh fa5, 18(a1)
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; CHECK-NEXT: fsh fa0, 18(a1)
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; CHECK-NEXT: ret
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%1 = fadd bfloat %a, %b
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%2 = load volatile bfloat, ptr @G
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store bfloat %1, ptr @G
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%3 = getelementptr bfloat, ptr @G, i32 9
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%4 = load volatile bfloat, ptr %3
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store bfloat %1, ptr %3
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ret bfloat %1
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}
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; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
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define bfloat @flh_fsh_constant(bfloat %a) nounwind {
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; RV32IZFBFMIN-LABEL: flh_fsh_constant:
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; RV32IZFBFMIN: # %bb.0:
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; RV32IZFBFMIN-NEXT: lui a0, 912092
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; RV32IZFBFMIN-NEXT: flh fa5, -273(a0)
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; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
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; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa5
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; RV32IZFBFMIN-NEXT: fadd.s fa5, fa4, fa5
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; RV32IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
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; RV32IZFBFMIN-NEXT: fsh fa0, -273(a0)
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; RV32IZFBFMIN-NEXT: ret
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;
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; RV64IZFBFMIN-LABEL: flh_fsh_constant:
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; RV64IZFBFMIN: # %bb.0:
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; RV64IZFBFMIN-NEXT: lui a0, 228023
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; RV64IZFBFMIN-NEXT: slli a0, a0, 2
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; RV64IZFBFMIN-NEXT: flh fa5, -273(a0)
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; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
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; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa5
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; RV64IZFBFMIN-NEXT: fadd.s fa5, fa4, fa5
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; RV64IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
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; RV64IZFBFMIN-NEXT: fsh fa0, -273(a0)
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; RV64IZFBFMIN-NEXT: ret
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%1 = inttoptr i32 3735928559 to ptr
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%2 = load volatile bfloat, ptr %1
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%3 = fadd bfloat %a, %2
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store bfloat %3, ptr %1
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ret bfloat %3
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}
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declare void @notdead(ptr)
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define bfloat @flh_stack(bfloat %a) nounwind {
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; RV32IZFBFMIN-LABEL: flh_stack:
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; RV32IZFBFMIN: # %bb.0:
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; RV32IZFBFMIN-NEXT: addi sp, sp, -16
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; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFBFMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
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; RV32IZFBFMIN-NEXT: fmv.s fs0, fa0
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; RV32IZFBFMIN-NEXT: addi a0, sp, 4
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; RV32IZFBFMIN-NEXT: call notdead
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; RV32IZFBFMIN-NEXT: flh fa5, 4(sp)
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; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fs0
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; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa5
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; RV32IZFBFMIN-NEXT: fadd.s fa5, fa5, fa4
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; RV32IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
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; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFBFMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
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; RV32IZFBFMIN-NEXT: addi sp, sp, 16
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; RV32IZFBFMIN-NEXT: ret
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;
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; RV64IZFBFMIN-LABEL: flh_stack:
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; RV64IZFBFMIN: # %bb.0:
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; RV64IZFBFMIN-NEXT: addi sp, sp, -16
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; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFBFMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
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; RV64IZFBFMIN-NEXT: fmv.s fs0, fa0
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; RV64IZFBFMIN-NEXT: mv a0, sp
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; RV64IZFBFMIN-NEXT: call notdead
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; RV64IZFBFMIN-NEXT: flh fa5, 0(sp)
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; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fs0
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; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa5
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; RV64IZFBFMIN-NEXT: fadd.s fa5, fa5, fa4
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; RV64IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
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; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFBFMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
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; RV64IZFBFMIN-NEXT: addi sp, sp, 16
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; RV64IZFBFMIN-NEXT: ret
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%1 = alloca bfloat, align 4
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call void @notdead(ptr %1)
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%2 = load bfloat, ptr %1
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%3 = fadd bfloat %2, %a ; force load in to FPR16
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ret bfloat %3
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}
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define dso_local void @fsh_stack(bfloat %a, bfloat %b) nounwind {
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; RV32IZFBFMIN-LABEL: fsh_stack:
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; RV32IZFBFMIN: # %bb.0:
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; RV32IZFBFMIN-NEXT: addi sp, sp, -16
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; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa1
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; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
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; RV32IZFBFMIN-NEXT: fadd.s fa5, fa4, fa5
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; RV32IZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
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; RV32IZFBFMIN-NEXT: fsh fa5, 8(sp)
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; RV32IZFBFMIN-NEXT: addi a0, sp, 8
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; RV32IZFBFMIN-NEXT: call notdead
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; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFBFMIN-NEXT: addi sp, sp, 16
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; RV32IZFBFMIN-NEXT: ret
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;
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; RV64IZFBFMIN-LABEL: fsh_stack:
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; RV64IZFBFMIN: # %bb.0:
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; RV64IZFBFMIN-NEXT: addi sp, sp, -16
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; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa1
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; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
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; RV64IZFBFMIN-NEXT: fadd.s fa5, fa4, fa5
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; RV64IZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
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; RV64IZFBFMIN-NEXT: fsh fa5, 4(sp)
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; RV64IZFBFMIN-NEXT: addi a0, sp, 4
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; RV64IZFBFMIN-NEXT: call notdead
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; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFBFMIN-NEXT: addi sp, sp, 16
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; RV64IZFBFMIN-NEXT: ret
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%1 = fadd bfloat %a, %b ; force store from FPR16
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%2 = alloca bfloat, align 4
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store bfloat %1, ptr %2
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call void @notdead(ptr %2)
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ret void
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}
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