188 lines
6.2 KiB
YAML
188 lines
6.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
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# RUN: | FileCheck -check-prefix=RV32I %s
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---
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name: brcond
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; RV32I-LABEL: name: brcond
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; RV32I: bb.0:
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; RV32I-NEXT: liveins: $x10, $x11, $x12
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
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; RV32I-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BEQ [[LW]], [[COPY]], %bb.14
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; RV32I-NEXT: PseudoBR %bb.1
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.1:
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; RV32I-NEXT: [[LW1:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BNE [[LW1]], [[COPY]], %bb.14
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; RV32I-NEXT: PseudoBR %bb.2
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.2:
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; RV32I-NEXT: [[LW2:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BLT [[LW2]], [[COPY]], %bb.14
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; RV32I-NEXT: PseudoBR %bb.3
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.3:
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; RV32I-NEXT: [[LW3:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BGE [[LW3]], [[COPY]], %bb.14
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; RV32I-NEXT: PseudoBR %bb.4
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.4:
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; RV32I-NEXT: [[LW4:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BLTU [[LW4]], [[COPY]], %bb.14
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; RV32I-NEXT: PseudoBR %bb.5
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.5:
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; RV32I-NEXT: [[LW5:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BGEU [[LW5]], [[COPY]], %bb.14
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; RV32I-NEXT: PseudoBR %bb.6
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.6:
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; RV32I-NEXT: [[LW6:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BLT [[COPY]], [[LW6]], %bb.14
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; RV32I-NEXT: PseudoBR %bb.7
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.7:
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; RV32I-NEXT: [[LW7:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BGE [[COPY]], [[LW7]], %bb.14
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; RV32I-NEXT: PseudoBR %bb.8
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.8:
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; RV32I-NEXT: [[LW8:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BLTU [[COPY]], [[LW8]], %bb.14
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; RV32I-NEXT: PseudoBR %bb.9
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.9:
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; RV32I-NEXT: [[LW9:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BGEU [[COPY]], [[LW9]], %bb.14
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; RV32I-NEXT: PseudoBR %bb.10
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.10:
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; RV32I-NEXT: [[LW10:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
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; RV32I-NEXT: BNE [[ANDI]], $x0, %bb.14
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; RV32I-NEXT: PseudoBR %bb.11
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.11:
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; RV32I-NEXT: successors: %bb.14(0x50000000), %bb.12(0x30000000)
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[LW11:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BGE [[LW11]], $x0, %bb.14
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; RV32I-NEXT: PseudoBR %bb.12
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.12:
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; RV32I-NEXT: successors: %bb.14(0x30000000), %bb.13(0x50000000)
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: [[LW12:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: BGE $x0, [[LW12]], %bb.14
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; RV32I-NEXT: PseudoBR %bb.13
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.13:
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; RV32I-NEXT: [[LW13:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (volatile load (s32))
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; RV32I-NEXT: {{ $}}
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; RV32I-NEXT: bb.14:
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; RV32I-NEXT: PseudoRET
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bb.1:
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liveins: $x10, $x11, $x12
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%0:gprb(s32) = COPY $x10
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%1:gprb(p0) = COPY $x11
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%3:gprb(s32) = COPY $x12
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%26:gprb(s32) = G_CONSTANT i32 -1
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%29:gprb(s32) = G_CONSTANT i32 1
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%4:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%56:gprb(s32) = G_ICMP intpred(eq), %4(s32), %0
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G_BRCOND %56(s32), %bb.15
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G_BR %bb.2
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bb.2:
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%6:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%54:gprb(s32) = G_ICMP intpred(ne), %6(s32), %0
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G_BRCOND %54(s32), %bb.15
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G_BR %bb.3
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bb.3:
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%8:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%52:gprb(s32) = G_ICMP intpred(slt), %8(s32), %0
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G_BRCOND %52(s32), %bb.15
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G_BR %bb.4
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bb.4:
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%10:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%50:gprb(s32) = G_ICMP intpred(sge), %10(s32), %0
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G_BRCOND %50(s32), %bb.15
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G_BR %bb.5
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bb.5:
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%12:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%48:gprb(s32) = G_ICMP intpred(ult), %12(s32), %0
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G_BRCOND %48(s32), %bb.15
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G_BR %bb.6
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bb.6:
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%14:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%46:gprb(s32) = G_ICMP intpred(uge), %14(s32), %0
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G_BRCOND %46(s32), %bb.15
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G_BR %bb.7
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bb.7:
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%16:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%44:gprb(s32) = G_ICMP intpred(sgt), %16(s32), %0
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G_BRCOND %44(s32), %bb.15
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G_BR %bb.8
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bb.8:
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%18:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%42:gprb(s32) = G_ICMP intpred(sle), %18(s32), %0
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G_BRCOND %42(s32), %bb.15
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G_BR %bb.9
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bb.9:
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%20:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%40:gprb(s32) = G_ICMP intpred(ugt), %20(s32), %0
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G_BRCOND %40(s32), %bb.15
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G_BR %bb.10
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bb.10:
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%22:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%38:gprb(s32) = G_ICMP intpred(ule), %22(s32), %0
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G_BRCOND %38(s32), %bb.15
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G_BR %bb.11
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bb.11:
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%24:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%57:gprb(s32) = G_CONSTANT i32 1
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%36:gprb(s32) = G_AND %3, %57
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G_BRCOND %36(s32), %bb.15
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G_BR %bb.12
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bb.12:
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successors: %bb.15(0x50000000), %bb.13(0x30000000)
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%25:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%35:gprb(s32) = G_ICMP intpred(sgt), %25(s32), %26
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G_BRCOND %35(s32), %bb.15
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G_BR %bb.13
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bb.13:
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successors: %bb.15(0x30000000), %bb.14(0x50000000)
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%28:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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%33:gprb(s32) = G_ICMP intpred(slt), %28(s32), %29
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G_BRCOND %33(s32), %bb.15
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G_BR %bb.14
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bb.14:
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%31:gprb(s32) = G_LOAD %1(p0) :: (volatile load (s32))
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bb.15:
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PseudoRET
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...
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