328 lines
11 KiB
C++
328 lines
11 KiB
C++
//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone enum definitions for the RISC-V target
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// useful for the compiler back-end and the MC libraries.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVBaseInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/RISCVISAInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TargetParser/TargetParser.h"
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#include "llvm/TargetParser/Triple.h"
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namespace llvm {
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extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
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namespace RISCVSysReg {
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#define GET_SysRegsList_IMPL
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#include "RISCVGenSearchableTables.inc"
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} // namespace RISCVSysReg
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namespace RISCVInsnOpcode {
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#define GET_RISCVOpcodesList_IMPL
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#include "RISCVGenSearchableTables.inc"
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} // namespace RISCVInsnOpcode
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namespace RISCVABI {
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ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
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StringRef ABIName) {
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auto TargetABI = getTargetABI(ABIName);
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bool IsRV64 = TT.isArch64Bit();
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bool IsRVE = FeatureBits[RISCV::FeatureRVE];
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if (!ABIName.empty() && TargetABI == ABI_Unknown) {
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errs()
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<< "'" << ABIName
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<< "' is not a recognized ABI for this target (ignoring target-abi)\n";
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} else if (ABIName.starts_with("ilp32") && IsRV64) {
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errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
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"target-abi)\n";
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TargetABI = ABI_Unknown;
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} else if (ABIName.starts_with("lp64") && !IsRV64) {
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errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
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"target-abi)\n";
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TargetABI = ABI_Unknown;
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} else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E &&
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TargetABI != ABI_Unknown) {
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// TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
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errs()
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<< "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
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TargetABI = ABI_Unknown;
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} else if (IsRV64 && IsRVE && TargetABI != ABI_LP64E &&
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TargetABI != ABI_Unknown) {
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// TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
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errs()
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<< "Only the lp64e ABI is supported for RV64E (ignoring target-abi)\n";
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TargetABI = ABI_Unknown;
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}
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if ((TargetABI == RISCVABI::ABI::ABI_ILP32E ||
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(TargetABI == ABI_Unknown && IsRVE && !IsRV64)) &&
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FeatureBits[RISCV::FeatureStdExtD])
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report_fatal_error("ILP32E cannot be used with the D ISA extension");
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if (TargetABI != ABI_Unknown)
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return TargetABI;
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// If no explicit ABI is given, try to compute the default ABI.
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auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
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if (!ISAInfo)
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report_fatal_error(ISAInfo.takeError());
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return getTargetABI((*ISAInfo)->computeDefaultABI());
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}
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ABI getTargetABI(StringRef ABIName) {
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auto TargetABI = StringSwitch<ABI>(ABIName)
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.Case("ilp32", ABI_ILP32)
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.Case("ilp32f", ABI_ILP32F)
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.Case("ilp32d", ABI_ILP32D)
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.Case("ilp32e", ABI_ILP32E)
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.Case("lp64", ABI_LP64)
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.Case("lp64f", ABI_LP64F)
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.Case("lp64d", ABI_LP64D)
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.Case("lp64e", ABI_LP64E)
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.Default(ABI_Unknown);
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return TargetABI;
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}
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// To avoid the BP value clobbered by a function call, we need to choose a
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// callee saved register to save the value. RV32E only has X8 and X9 as callee
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// saved registers and X8 will be used as fp. So we choose X9 as bp.
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MCRegister getBPReg() { return RISCV::X9; }
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// Returns the register holding shadow call stack pointer.
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MCRegister getSCSPReg() { return RISCV::X3; }
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} // namespace RISCVABI
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namespace RISCVFeatures {
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void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
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if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
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report_fatal_error("RV64 target requires an RV64 CPU");
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if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
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report_fatal_error("RV32 target requires an RV32 CPU");
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if (FeatureBits[RISCV::Feature32Bit] &&
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FeatureBits[RISCV::Feature64Bit])
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report_fatal_error("RV32 and RV64 can't be combined");
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}
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llvm::Expected<std::unique_ptr<RISCVISAInfo>>
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parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
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unsigned XLen = IsRV64 ? 64 : 32;
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std::vector<std::string> FeatureVector;
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// Convert FeatureBitset to FeatureVector.
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for (auto Feature : RISCVFeatureKV) {
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if (FeatureBits[Feature.Value] &&
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llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key))
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FeatureVector.push_back(std::string("+") + Feature.Key);
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}
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return llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
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}
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} // namespace RISCVFeatures
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// Encode VTYPE into the binary format used by the the VSETVLI instruction which
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// is used by our MC layer representation.
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//
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// Bits | Name | Description
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// -----+------------+------------------------------------------------
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// 7 | vma | Vector mask agnostic
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// 6 | vta | Vector tail agnostic
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// 5:3 | vsew[2:0] | Standard element width (SEW) setting
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// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting
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unsigned RISCVVType::encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW,
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bool TailAgnostic, bool MaskAgnostic) {
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assert(isValidSEW(SEW) && "Invalid SEW");
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unsigned VLMULBits = static_cast<unsigned>(VLMUL);
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unsigned VSEWBits = encodeSEW(SEW);
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unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7);
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if (TailAgnostic)
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VTypeI |= 0x40;
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if (MaskAgnostic)
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VTypeI |= 0x80;
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return VTypeI;
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}
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std::pair<unsigned, bool> RISCVVType::decodeVLMUL(RISCVII::VLMUL VLMUL) {
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switch (VLMUL) {
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default:
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llvm_unreachable("Unexpected LMUL value!");
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case RISCVII::VLMUL::LMUL_1:
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case RISCVII::VLMUL::LMUL_2:
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case RISCVII::VLMUL::LMUL_4:
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case RISCVII::VLMUL::LMUL_8:
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return std::make_pair(1 << static_cast<unsigned>(VLMUL), false);
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case RISCVII::VLMUL::LMUL_F2:
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case RISCVII::VLMUL::LMUL_F4:
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case RISCVII::VLMUL::LMUL_F8:
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return std::make_pair(1 << (8 - static_cast<unsigned>(VLMUL)), true);
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}
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}
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void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
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unsigned Sew = getSEW(VType);
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OS << "e" << Sew;
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unsigned LMul;
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bool Fractional;
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std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType));
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if (Fractional)
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OS << ", mf";
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else
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OS << ", m";
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OS << LMul;
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if (isTailAgnostic(VType))
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OS << ", ta";
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else
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OS << ", tu";
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if (isMaskAgnostic(VType))
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OS << ", ma";
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else
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OS << ", mu";
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}
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unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) {
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unsigned LMul;
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bool Fractional;
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std::tie(LMul, Fractional) = decodeVLMUL(VLMul);
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// Convert LMul to a fixed point value with 3 fractional bits.
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LMul = Fractional ? (8 / LMul) : (LMul * 8);
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assert(SEW >= 8 && "Unexpected SEW value");
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return (SEW * 8) / LMul;
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}
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std::optional<RISCVII::VLMUL>
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RISCVVType::getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW) {
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unsigned Ratio = RISCVVType::getSEWLMULRatio(SEW, VLMUL);
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unsigned EMULFixedPoint = (EEW * 8) / Ratio;
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bool Fractional = EMULFixedPoint < 8;
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unsigned EMUL = Fractional ? 8 / EMULFixedPoint : EMULFixedPoint / 8;
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if (!isValidLMUL(EMUL, Fractional))
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return std::nullopt;
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return RISCVVType::encodeLMUL(EMUL, Fractional);
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}
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// Include the auto-generated portion of the compress emitter.
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#define GEN_UNCOMPRESS_INSTR
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#define GEN_COMPRESS_INSTR
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#include "RISCVGenCompressInstEmitter.inc"
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bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI,
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const MCSubtargetInfo &STI) {
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return compressInst(OutInst, MI, STI);
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}
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bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI,
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const MCSubtargetInfo &STI) {
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return uncompressInst(OutInst, MI, STI);
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}
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// Lookup table for fli.s for entries 2-31.
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static constexpr std::pair<uint8_t, uint8_t> LoadFP32ImmArr[] = {
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{0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},
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{0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},
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{0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},
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{0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},
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{0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},
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{0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},
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{0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},
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{0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},
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{0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},
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{0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},
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};
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int RISCVLoadFPImm::getLoadFPImm(APFloat FPImm) {
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assert((&FPImm.getSemantics() == &APFloat::IEEEsingle() ||
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&FPImm.getSemantics() == &APFloat::IEEEdouble() ||
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&FPImm.getSemantics() == &APFloat::IEEEhalf()) &&
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"Unexpected semantics");
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// Handle the minimum normalized value which is different for each type.
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if (FPImm.isSmallestNormalized() && !FPImm.isNegative())
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return 1;
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// Convert to single precision to use its lookup table.
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bool LosesInfo;
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APFloat::opStatus Status = FPImm.convert(
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APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &LosesInfo);
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if (Status != APFloat::opOK || LosesInfo)
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return -1;
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APInt Imm = FPImm.bitcastToAPInt();
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if (Imm.extractBitsAsZExtValue(21, 0) != 0)
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return -1;
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bool Sign = Imm.extractBitsAsZExtValue(1, 31);
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uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21);
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uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23);
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auto EMI = llvm::lower_bound(LoadFP32ImmArr, std::make_pair(Exp, Mantissa));
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if (EMI == std::end(LoadFP32ImmArr) || EMI->first != Exp ||
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EMI->second != Mantissa)
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return -1;
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// Table doesn't have entry 0 or 1.
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int Entry = std::distance(std::begin(LoadFP32ImmArr), EMI) + 2;
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// The only legal negative value is -1.0(entry 0). 1.0 is entry 16.
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if (Sign) {
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if (Entry == 16)
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return 0;
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return -1;
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}
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return Entry;
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}
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float RISCVLoadFPImm::getFPImm(unsigned Imm) {
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assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate");
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// Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
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uint32_t Sign = 0;
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if (Imm == 0) {
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Sign = 0b1;
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Imm = 16;
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}
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uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
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uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
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uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
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return bit_cast<float>(I);
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}
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void RISCVZC::printRlist(unsigned SlistEncode, raw_ostream &OS) {
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OS << "{ra";
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if (SlistEncode > 4) {
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OS << ", s0";
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if (SlistEncode == 15)
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OS << "-s11";
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else if (SlistEncode > 5 && SlistEncode <= 14)
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OS << "-s" << (SlistEncode - 5);
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}
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OS << "}";
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}
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void RISCVZC::printSpimm(int64_t Spimm, raw_ostream &OS) { OS << Spimm; }
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} // namespace llvm
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