667 lines
19 KiB
C++
667 lines
19 KiB
C++
//===-- RISCVBaseInfo.h - Top level definitions for RISC-V MC ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone enum definitions for the RISC-V target
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// useful for the compiler back-end and the MC libraries.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/RISCVISAInfo.h"
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#include "llvm/TargetParser/SubtargetFeature.h"
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namespace llvm {
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// RISCVII - This namespace holds all of the target specific flags that
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// instruction info tracks. All definitions must match RISCVInstrFormats.td.
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namespace RISCVII {
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enum {
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InstFormatPseudo = 0,
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InstFormatR = 1,
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InstFormatR4 = 2,
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InstFormatI = 3,
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InstFormatS = 4,
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InstFormatB = 5,
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InstFormatU = 6,
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InstFormatJ = 7,
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InstFormatCR = 8,
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InstFormatCI = 9,
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InstFormatCSS = 10,
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InstFormatCIW = 11,
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InstFormatCL = 12,
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InstFormatCS = 13,
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InstFormatCA = 14,
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InstFormatCB = 15,
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InstFormatCJ = 16,
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InstFormatCU = 17,
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InstFormatCLB = 18,
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InstFormatCLH = 19,
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InstFormatCSB = 20,
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InstFormatCSH = 21,
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InstFormatOther = 22,
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InstFormatMask = 31,
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InstFormatShift = 0,
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ConstraintShift = InstFormatShift + 5,
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VS2Constraint = 0b001 << ConstraintShift,
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VS1Constraint = 0b010 << ConstraintShift,
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VMConstraint = 0b100 << ConstraintShift,
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ConstraintMask = 0b111 << ConstraintShift,
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VLMulShift = ConstraintShift + 3,
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VLMulMask = 0b111 << VLMulShift,
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// Force a tail agnostic policy even this instruction has a tied destination.
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ForceTailAgnosticShift = VLMulShift + 3,
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ForceTailAgnosticMask = 1 << ForceTailAgnosticShift,
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// Is this a _TIED vector pseudo instruction. For these instructions we
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// shouldn't skip the tied operand when converting to MC instructions.
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IsTiedPseudoShift = ForceTailAgnosticShift + 1,
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IsTiedPseudoMask = 1 << IsTiedPseudoShift,
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// Does this instruction have a SEW operand. It will be the last explicit
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// operand unless there is a vector policy operand. Used by RVV Pseudos.
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HasSEWOpShift = IsTiedPseudoShift + 1,
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HasSEWOpMask = 1 << HasSEWOpShift,
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// Does this instruction have a VL operand. It will be the second to last
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// explicit operand unless there is a vector policy operand. Used by RVV
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// Pseudos.
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HasVLOpShift = HasSEWOpShift + 1,
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HasVLOpMask = 1 << HasVLOpShift,
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// Does this instruction have a vector policy operand. It will be the last
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// explicit operand. Used by RVV Pseudos.
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HasVecPolicyOpShift = HasVLOpShift + 1,
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HasVecPolicyOpMask = 1 << HasVecPolicyOpShift,
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// Is this instruction a vector widening reduction instruction. Used by RVV
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// Pseudos.
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IsRVVWideningReductionShift = HasVecPolicyOpShift + 1,
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IsRVVWideningReductionMask = 1 << IsRVVWideningReductionShift,
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// Does this instruction care about mask policy. If it is not, the mask policy
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// could be either agnostic or undisturbed. For example, unmasked, store, and
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// reduction operations result would not be affected by mask policy, so
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// compiler has free to select either one.
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UsesMaskPolicyShift = IsRVVWideningReductionShift + 1,
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UsesMaskPolicyMask = 1 << UsesMaskPolicyShift,
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// Indicates that the result can be considered sign extended from bit 31. Some
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// instructions with this flag aren't W instructions, but are either sign
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// extended from a smaller size, always outputs a small integer, or put zeros
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// in bits 63:31. Used by the SExtWRemoval pass.
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IsSignExtendingOpWShift = UsesMaskPolicyShift + 1,
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IsSignExtendingOpWMask = 1ULL << IsSignExtendingOpWShift,
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HasRoundModeOpShift = IsSignExtendingOpWShift + 1,
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HasRoundModeOpMask = 1 << HasRoundModeOpShift,
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UsesVXRMShift = HasRoundModeOpShift + 1,
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UsesVXRMMask = 1 << UsesVXRMShift,
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// Indicates whether these instructions can partially overlap between source
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// registers and destination registers according to the vector spec.
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// 0 -> not a vector pseudo
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// 1 -> default value for vector pseudos. not widening or narrowing.
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// 2 -> narrowing case
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// 3 -> widening case
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TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
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TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
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};
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enum VLMUL : uint8_t {
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LMUL_1 = 0,
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LMUL_2,
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LMUL_4,
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LMUL_8,
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LMUL_RESERVED,
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LMUL_F8,
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LMUL_F4,
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LMUL_F2
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};
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enum {
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TAIL_UNDISTURBED_MASK_UNDISTURBED = 0,
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TAIL_AGNOSTIC = 1,
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MASK_AGNOSTIC = 2,
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};
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// Helper functions to read TSFlags.
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/// \returns the format of the instruction.
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static inline unsigned getFormat(uint64_t TSFlags) {
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return (TSFlags & InstFormatMask) >> InstFormatShift;
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}
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/// \returns the LMUL for the instruction.
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static inline VLMUL getLMul(uint64_t TSFlags) {
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return static_cast<VLMUL>((TSFlags & VLMulMask) >> VLMulShift);
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}
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/// \returns true if tail agnostic is enforced for the instruction.
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static inline bool doesForceTailAgnostic(uint64_t TSFlags) {
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return TSFlags & ForceTailAgnosticMask;
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}
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/// \returns true if this a _TIED pseudo.
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static inline bool isTiedPseudo(uint64_t TSFlags) {
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return TSFlags & IsTiedPseudoMask;
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}
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/// \returns true if there is a SEW operand for the instruction.
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static inline bool hasSEWOp(uint64_t TSFlags) {
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return TSFlags & HasSEWOpMask;
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}
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/// \returns true if there is a VL operand for the instruction.
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static inline bool hasVLOp(uint64_t TSFlags) {
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return TSFlags & HasVLOpMask;
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}
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/// \returns true if there is a vector policy operand for this instruction.
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static inline bool hasVecPolicyOp(uint64_t TSFlags) {
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return TSFlags & HasVecPolicyOpMask;
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}
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/// \returns true if it is a vector widening reduction instruction.
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static inline bool isRVVWideningReduction(uint64_t TSFlags) {
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return TSFlags & IsRVVWideningReductionMask;
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}
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/// \returns true if mask policy is valid for the instruction.
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static inline bool usesMaskPolicy(uint64_t TSFlags) {
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return TSFlags & UsesMaskPolicyMask;
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}
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/// \returns true if there is a rounding mode operand for this instruction
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static inline bool hasRoundModeOp(uint64_t TSFlags) {
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return TSFlags & HasRoundModeOpMask;
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}
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/// \returns true if this instruction uses vxrm
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static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
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static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
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const uint64_t TSFlags = Desc.TSFlags;
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// This method is only called if we expect to have a VL operand, and all
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// instructions with VL also have SEW.
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assert(hasSEWOp(TSFlags) && hasVLOp(TSFlags));
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unsigned Offset = 2;
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if (hasVecPolicyOp(TSFlags))
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Offset = 3;
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return Desc.getNumOperands() - Offset;
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}
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static inline unsigned getSEWOpNum(const MCInstrDesc &Desc) {
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const uint64_t TSFlags = Desc.TSFlags;
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assert(hasSEWOp(TSFlags));
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unsigned Offset = 1;
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if (hasVecPolicyOp(TSFlags))
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Offset = 2;
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return Desc.getNumOperands() - Offset;
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}
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static inline unsigned getVecPolicyOpNum(const MCInstrDesc &Desc) {
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assert(hasVecPolicyOp(Desc.TSFlags));
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return Desc.getNumOperands() - 1;
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}
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/// \returns the index to the rounding mode immediate value if any, otherwise
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/// returns -1.
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static inline int getFRMOpNum(const MCInstrDesc &Desc) {
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const uint64_t TSFlags = Desc.TSFlags;
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if (!hasRoundModeOp(TSFlags) || usesVXRM(TSFlags))
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return -1;
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// The operand order
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// --------------------------------------
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// | n-1 (if any) | n-2 | n-3 | n-4 |
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// | policy | sew | vl | frm |
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// --------------------------------------
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return getVLOpNum(Desc) - 1;
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}
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/// \returns the index to the rounding mode immediate value if any, otherwise
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/// returns -1.
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static inline int getVXRMOpNum(const MCInstrDesc &Desc) {
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const uint64_t TSFlags = Desc.TSFlags;
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if (!hasRoundModeOp(TSFlags) || !usesVXRM(TSFlags))
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return -1;
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// The operand order
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// --------------------------------------
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// | n-1 (if any) | n-2 | n-3 | n-4 |
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// | policy | sew | vl | vxrm |
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// --------------------------------------
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return getVLOpNum(Desc) - 1;
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}
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// Is the first def operand tied to the first use operand. This is true for
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// vector pseudo instructions that have a merge operand for tail/mask
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// undisturbed. It's also true for vector FMA instructions where one of the
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// operands is also the destination register.
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static inline bool isFirstDefTiedToFirstUse(const MCInstrDesc &Desc) {
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return Desc.getNumDefs() < Desc.getNumOperands() &&
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Desc.getOperandConstraint(Desc.getNumDefs(), MCOI::TIED_TO) == 0;
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}
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// RISC-V Specific Machine Operand Flags
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enum {
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MO_None = 0,
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MO_CALL = 1,
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MO_LO = 3,
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MO_HI = 4,
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MO_PCREL_LO = 5,
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MO_PCREL_HI = 6,
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MO_GOT_HI = 7,
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MO_TPREL_LO = 8,
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MO_TPREL_HI = 9,
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MO_TPREL_ADD = 10,
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MO_TLS_GOT_HI = 11,
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MO_TLS_GD_HI = 12,
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MO_TLSDESC_HI = 13,
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MO_TLSDESC_LOAD_LO = 14,
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MO_TLSDESC_ADD_LO = 15,
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MO_TLSDESC_CALL = 16,
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// Used to differentiate between target-specific "direct" flags and "bitmask"
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// flags. A machine operand can only have one "direct" flag, but can have
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// multiple "bitmask" flags.
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MO_DIRECT_FLAG_MASK = 31
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};
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} // namespace RISCVII
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namespace RISCVOp {
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enum OperandType : unsigned {
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OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
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OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
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OPERAND_UIMM2,
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OPERAND_UIMM2_LSB0,
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OPERAND_UIMM3,
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OPERAND_UIMM4,
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OPERAND_UIMM5,
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OPERAND_UIMM6,
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OPERAND_UIMM7,
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OPERAND_UIMM7_LSB00,
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OPERAND_UIMM8_LSB00,
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OPERAND_UIMM8,
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OPERAND_UIMM8_LSB000,
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OPERAND_UIMM8_GE32,
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OPERAND_UIMM9_LSB000,
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OPERAND_UIMM10_LSB00_NONZERO,
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OPERAND_UIMM12,
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OPERAND_ZERO,
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OPERAND_SIMM5,
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OPERAND_SIMM5_PLUS1,
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OPERAND_SIMM6,
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OPERAND_SIMM6_NONZERO,
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OPERAND_SIMM10_LSB0000_NONZERO,
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OPERAND_SIMM12,
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OPERAND_SIMM12_LSB00000,
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OPERAND_UIMM20,
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OPERAND_UIMMLOG2XLEN,
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OPERAND_UIMMLOG2XLEN_NONZERO,
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OPERAND_CLUI_IMM,
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OPERAND_VTYPEI10,
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OPERAND_VTYPEI11,
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OPERAND_RVKRNUM,
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OPERAND_RVKRNUM_0_7,
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OPERAND_RVKRNUM_1_10,
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OPERAND_RVKRNUM_2_14,
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OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM_2_14,
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// Operand is either a register or uimm5, this is used by V extension pseudo
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// instructions to represent a value that be passed as AVL to either vsetvli
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// or vsetivli.
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OPERAND_AVL,
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};
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} // namespace RISCVOp
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// Describes the predecessor/successor bits used in the FENCE instruction.
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namespace RISCVFenceField {
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enum FenceField {
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I = 8,
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O = 4,
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R = 2,
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W = 1
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};
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}
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// Describes the supported floating point rounding mode encodings.
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namespace RISCVFPRndMode {
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enum RoundingMode {
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RNE = 0,
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RTZ = 1,
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RDN = 2,
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RUP = 3,
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RMM = 4,
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DYN = 7,
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Invalid
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};
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inline static StringRef roundingModeToString(RoundingMode RndMode) {
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switch (RndMode) {
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default:
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llvm_unreachable("Unknown floating point rounding mode");
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case RISCVFPRndMode::RNE:
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return "rne";
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case RISCVFPRndMode::RTZ:
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return "rtz";
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case RISCVFPRndMode::RDN:
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return "rdn";
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case RISCVFPRndMode::RUP:
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return "rup";
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case RISCVFPRndMode::RMM:
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return "rmm";
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case RISCVFPRndMode::DYN:
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return "dyn";
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}
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}
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inline static RoundingMode stringToRoundingMode(StringRef Str) {
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return StringSwitch<RoundingMode>(Str)
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.Case("rne", RISCVFPRndMode::RNE)
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.Case("rtz", RISCVFPRndMode::RTZ)
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.Case("rdn", RISCVFPRndMode::RDN)
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.Case("rup", RISCVFPRndMode::RUP)
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.Case("rmm", RISCVFPRndMode::RMM)
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.Case("dyn", RISCVFPRndMode::DYN)
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.Default(RISCVFPRndMode::Invalid);
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}
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inline static bool isValidRoundingMode(unsigned Mode) {
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switch (Mode) {
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default:
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return false;
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case RISCVFPRndMode::RNE:
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case RISCVFPRndMode::RTZ:
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case RISCVFPRndMode::RDN:
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case RISCVFPRndMode::RUP:
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case RISCVFPRndMode::RMM:
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case RISCVFPRndMode::DYN:
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return true;
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}
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}
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} // namespace RISCVFPRndMode
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//===----------------------------------------------------------------------===//
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// Floating-point Immediates
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//
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namespace RISCVLoadFPImm {
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float getFPImm(unsigned Imm);
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/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
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/// immediate value. If the value cannot be represented as a 5-bit binary
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/// encoding, then return -1.
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int getLoadFPImm(APFloat FPImm);
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} // namespace RISCVLoadFPImm
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namespace RISCVSysReg {
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struct SysReg {
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const char *Name;
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const char *AltName;
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const char *DeprecatedName;
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unsigned Encoding;
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// FIXME: add these additional fields when needed.
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// Privilege Access: Read, Write, Read-Only.
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// unsigned ReadWrite;
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// Privilege Mode: User, System or Machine.
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// unsigned Mode;
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// Check field name.
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// unsigned Extra;
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// Register number without the privilege bits.
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// unsigned Number;
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FeatureBitset FeaturesRequired;
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bool isRV32Only;
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bool haveRequiredFeatures(const FeatureBitset &ActiveFeatures) const {
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// Not in 32-bit mode.
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if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
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return false;
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// No required feature associated with the system register.
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if (FeaturesRequired.none())
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return true;
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return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
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}
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};
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#define GET_SysRegsList_DECL
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#include "RISCVGenSearchableTables.inc"
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} // end namespace RISCVSysReg
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namespace RISCVInsnOpcode {
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struct RISCVOpcode {
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const char *Name;
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unsigned Value;
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};
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#define GET_RISCVOpcodesList_DECL
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#include "RISCVGenSearchableTables.inc"
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} // end namespace RISCVInsnOpcode
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namespace RISCVABI {
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enum ABI {
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ABI_ILP32,
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ABI_ILP32F,
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ABI_ILP32D,
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ABI_ILP32E,
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ABI_LP64,
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ABI_LP64F,
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ABI_LP64D,
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ABI_LP64E,
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ABI_Unknown
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};
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// Returns the target ABI, or else a StringError if the requested ABIName is
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// not supported for the given TT and FeatureBits combination.
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ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
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StringRef ABIName);
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ABI getTargetABI(StringRef ABIName);
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// Returns the register used to hold the stack pointer after realignment.
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MCRegister getBPReg();
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// Returns the register holding shadow call stack pointer.
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MCRegister getSCSPReg();
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} // namespace RISCVABI
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namespace RISCVFeatures {
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// Validates if the given combination of features are valid for the target
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// triple. Exits with report_fatal_error if not.
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void validate(const Triple &TT, const FeatureBitset &FeatureBits);
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llvm::Expected<std::unique_ptr<RISCVISAInfo>>
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parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
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} // namespace RISCVFeatures
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namespace RISCVVType {
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// Is this a SEW value that can be encoded into the VTYPE format.
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inline static bool isValidSEW(unsigned SEW) {
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return isPowerOf2_32(SEW) && SEW >= 8 && SEW <= 1024;
|
|
}
|
|
|
|
// Is this a LMUL value that can be encoded into the VTYPE format.
|
|
inline static bool isValidLMUL(unsigned LMUL, bool Fractional) {
|
|
return isPowerOf2_32(LMUL) && LMUL <= 8 && (!Fractional || LMUL != 1);
|
|
}
|
|
|
|
unsigned encodeVTYPE(RISCVII::VLMUL VLMUL, unsigned SEW, bool TailAgnostic,
|
|
bool MaskAgnostic);
|
|
|
|
inline static RISCVII::VLMUL getVLMUL(unsigned VType) {
|
|
unsigned VLMUL = VType & 0x7;
|
|
return static_cast<RISCVII::VLMUL>(VLMUL);
|
|
}
|
|
|
|
// Decode VLMUL into 1,2,4,8 and fractional indicator.
|
|
std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
|
|
|
|
inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
|
|
assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
|
|
unsigned LmulLog2 = Log2_32(LMUL);
|
|
return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
|
|
}
|
|
|
|
inline static unsigned decodeVSEW(unsigned VSEW) {
|
|
assert(VSEW < 8 && "Unexpected VSEW value");
|
|
return 1 << (VSEW + 3);
|
|
}
|
|
|
|
inline static unsigned encodeSEW(unsigned SEW) {
|
|
assert(isValidSEW(SEW) && "Unexpected SEW value");
|
|
return Log2_32(SEW) - 3;
|
|
}
|
|
|
|
inline static unsigned getSEW(unsigned VType) {
|
|
unsigned VSEW = (VType >> 3) & 0x7;
|
|
return decodeVSEW(VSEW);
|
|
}
|
|
|
|
inline static bool isTailAgnostic(unsigned VType) { return VType & 0x40; }
|
|
|
|
inline static bool isMaskAgnostic(unsigned VType) { return VType & 0x80; }
|
|
|
|
void printVType(unsigned VType, raw_ostream &OS);
|
|
|
|
unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul);
|
|
|
|
std::optional<RISCVII::VLMUL>
|
|
getSameRatioLMUL(unsigned SEW, RISCVII::VLMUL VLMUL, unsigned EEW);
|
|
} // namespace RISCVVType
|
|
|
|
namespace RISCVRVC {
|
|
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
|
|
bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI);
|
|
} // namespace RISCVRVC
|
|
|
|
namespace RISCVZC {
|
|
enum RLISTENCODE {
|
|
RA = 4,
|
|
RA_S0,
|
|
RA_S0_S1,
|
|
RA_S0_S2,
|
|
RA_S0_S3,
|
|
RA_S0_S4,
|
|
RA_S0_S5,
|
|
RA_S0_S6,
|
|
RA_S0_S7,
|
|
RA_S0_S8,
|
|
RA_S0_S9,
|
|
// note - to include s10, s11 must also be included
|
|
RA_S0_S11,
|
|
INVALID_RLIST,
|
|
};
|
|
|
|
inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
|
|
assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
|
|
switch (EndReg) {
|
|
case RISCV::X1:
|
|
return RLISTENCODE::RA;
|
|
case RISCV::X8:
|
|
return RLISTENCODE::RA_S0;
|
|
case RISCV::X9:
|
|
return RLISTENCODE::RA_S0_S1;
|
|
case RISCV::X18:
|
|
return RLISTENCODE::RA_S0_S2;
|
|
case RISCV::X19:
|
|
return RLISTENCODE::RA_S0_S3;
|
|
case RISCV::X20:
|
|
return RLISTENCODE::RA_S0_S4;
|
|
case RISCV::X21:
|
|
return RLISTENCODE::RA_S0_S5;
|
|
case RISCV::X22:
|
|
return RLISTENCODE::RA_S0_S6;
|
|
case RISCV::X23:
|
|
return RLISTENCODE::RA_S0_S7;
|
|
case RISCV::X24:
|
|
return RLISTENCODE::RA_S0_S8;
|
|
case RISCV::X25:
|
|
return RLISTENCODE::RA_S0_S9;
|
|
case RISCV::X26:
|
|
return RLISTENCODE::INVALID_RLIST;
|
|
case RISCV::X27:
|
|
return RLISTENCODE::RA_S0_S11;
|
|
default:
|
|
llvm_unreachable("Undefined input.");
|
|
}
|
|
}
|
|
|
|
inline static unsigned getStackAdjBase(unsigned RlistVal, bool IsRV64,
|
|
bool IsEABI) {
|
|
assert(RlistVal != RLISTENCODE::INVALID_RLIST &&
|
|
"{ra, s0-s10} is not supported, s11 must be included.");
|
|
if (IsEABI)
|
|
return 16;
|
|
if (!IsRV64) {
|
|
switch (RlistVal) {
|
|
case RLISTENCODE::RA:
|
|
case RLISTENCODE::RA_S0:
|
|
case RLISTENCODE::RA_S0_S1:
|
|
case RLISTENCODE::RA_S0_S2:
|
|
return 16;
|
|
case RLISTENCODE::RA_S0_S3:
|
|
case RLISTENCODE::RA_S0_S4:
|
|
case RLISTENCODE::RA_S0_S5:
|
|
case RLISTENCODE::RA_S0_S6:
|
|
return 32;
|
|
case RLISTENCODE::RA_S0_S7:
|
|
case RLISTENCODE::RA_S0_S8:
|
|
case RLISTENCODE::RA_S0_S9:
|
|
return 48;
|
|
case RLISTENCODE::RA_S0_S11:
|
|
return 64;
|
|
}
|
|
} else {
|
|
switch (RlistVal) {
|
|
case RLISTENCODE::RA:
|
|
case RLISTENCODE::RA_S0:
|
|
return 16;
|
|
case RLISTENCODE::RA_S0_S1:
|
|
case RLISTENCODE::RA_S0_S2:
|
|
return 32;
|
|
case RLISTENCODE::RA_S0_S3:
|
|
case RLISTENCODE::RA_S0_S4:
|
|
return 48;
|
|
case RLISTENCODE::RA_S0_S5:
|
|
case RLISTENCODE::RA_S0_S6:
|
|
return 64;
|
|
case RLISTENCODE::RA_S0_S7:
|
|
case RLISTENCODE::RA_S0_S8:
|
|
return 80;
|
|
case RLISTENCODE::RA_S0_S9:
|
|
return 96;
|
|
case RLISTENCODE::RA_S0_S11:
|
|
return 112;
|
|
}
|
|
}
|
|
llvm_unreachable("Unexpected RlistVal");
|
|
}
|
|
|
|
inline static bool getSpimm(unsigned RlistVal, unsigned &SpimmVal,
|
|
int64_t StackAdjustment, bool IsRV64, bool IsEABI) {
|
|
if (RlistVal == RLISTENCODE::INVALID_RLIST)
|
|
return false;
|
|
unsigned stackAdj = getStackAdjBase(RlistVal, IsRV64, IsEABI);
|
|
SpimmVal = (StackAdjustment - stackAdj) / 16;
|
|
if (SpimmVal > 3)
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
void printRlist(unsigned SlistEncode, raw_ostream &OS);
|
|
void printSpimm(int64_t Spimm, raw_ostream &OS);
|
|
} // namespace RISCVZC
|
|
|
|
} // namespace llvm
|
|
|
|
#endif
|