112 lines
4.3 KiB
C++
112 lines
4.3 KiB
C++
//===-- RISCVFixupKinds.h - RISC-V Specific Fixup Entries -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/MC/MCFixup.h"
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#include <utility>
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#undef RISCV
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namespace llvm::RISCV {
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enum Fixups {
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// 20-bit fixup corresponding to %hi(foo) for instructions like lui
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fixup_riscv_hi20 = FirstTargetFixupKind,
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// 12-bit fixup corresponding to %lo(foo) for instructions like addi
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fixup_riscv_lo12_i,
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// 12-bit fixup corresponding to foo-bar for instructions like addi
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fixup_riscv_12_i,
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// 12-bit fixup corresponding to %lo(foo) for the S-type store instructions
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fixup_riscv_lo12_s,
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// 20-bit fixup corresponding to %pcrel_hi(foo) for instructions like auipc
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fixup_riscv_pcrel_hi20,
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// 12-bit fixup corresponding to %pcrel_lo(foo) for instructions like addi
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fixup_riscv_pcrel_lo12_i,
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// 12-bit fixup corresponding to %pcrel_lo(foo) for the S-type store
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// instructions
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fixup_riscv_pcrel_lo12_s,
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// 20-bit fixup corresponding to %got_pcrel_hi(foo) for instructions like
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// auipc
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fixup_riscv_got_hi20,
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// 20-bit fixup corresponding to %tprel_hi(foo) for instructions like lui
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fixup_riscv_tprel_hi20,
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// 12-bit fixup corresponding to %tprel_lo(foo) for instructions like addi
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fixup_riscv_tprel_lo12_i,
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// 12-bit fixup corresponding to %tprel_lo(foo) for the S-type store
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// instructions
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fixup_riscv_tprel_lo12_s,
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// Fixup corresponding to %tprel_add(foo) for PseudoAddTPRel, used as a linker
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// hint
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fixup_riscv_tprel_add,
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// 20-bit fixup corresponding to %tls_ie_pcrel_hi(foo) for instructions like
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// auipc
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fixup_riscv_tls_got_hi20,
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// 20-bit fixup corresponding to %tls_gd_pcrel_hi(foo) for instructions like
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// auipc
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fixup_riscv_tls_gd_hi20,
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// 20-bit fixup for symbol references in the jal instruction
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fixup_riscv_jal,
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// 12-bit fixup for symbol references in the branch instructions
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fixup_riscv_branch,
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// 11-bit fixup for symbol references in the compressed jump instruction
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fixup_riscv_rvc_jump,
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// 8-bit fixup for symbol references in the compressed branch instruction
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fixup_riscv_rvc_branch,
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// Fixup representing a legacy no-pic function call attached to the auipc
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// instruction in a pair composed of adjacent auipc+jalr instructions.
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fixup_riscv_call,
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// Fixup representing a function call attached to the auipc instruction in a
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// pair composed of adjacent auipc+jalr instructions.
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fixup_riscv_call_plt,
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// Used to generate an R_RISCV_RELAX relocation, which indicates the linker
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// may relax the instruction pair.
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fixup_riscv_relax,
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// Used to generate an R_RISCV_ALIGN relocation, which indicates the linker
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// should fixup the alignment after linker relaxation.
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fixup_riscv_align,
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// Fixups indicating a TLS descriptor code sequence, corresponding to auipc,
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// lw/ld, addi, and jalr, respectively.
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fixup_riscv_tlsdesc_hi20,
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fixup_riscv_tlsdesc_load_lo12,
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fixup_riscv_tlsdesc_add_lo12,
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fixup_riscv_tlsdesc_call,
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// Used as a sentinel, must be the last
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fixup_riscv_invalid,
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NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind
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};
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static inline std::pair<MCFixupKind, MCFixupKind>
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getRelocPairForSize(unsigned Size) {
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switch (Size) {
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default:
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llvm_unreachable("unsupported fixup size");
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case 1:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD8),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB8));
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case 2:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD16),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB16));
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case 4:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD32),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB32));
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case 8:
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return std::make_pair(
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_ADD64),
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MCFixupKind(FirstLiteralRelocationKind + ELF::R_RISCV_SUB64));
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}
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}
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} // end namespace llvm::RISCV
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#endif
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