354 lines
11 KiB
C++
354 lines
11 KiB
C++
//===-- RISCVMCTargetDesc.cpp - RISC-V Target Descriptions ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This file provides RISC-V specific target descriptions.
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///
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//===----------------------------------------------------------------------===//
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#include "RISCVMCTargetDesc.h"
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#include "RISCVBaseInfo.h"
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#include "RISCVELFStreamer.h"
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#include "RISCVInstPrinter.h"
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#include "RISCVMCAsmInfo.h"
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#include "RISCVMCObjectFileInfo.h"
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#include "RISCVTargetStreamer.h"
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#include "TargetInfo/RISCVTargetInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCObjectFileInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <bitset>
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#define GET_INSTRINFO_MC_DESC
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#define ENABLE_INSTR_PREDICATE_VERIFIER
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#include "RISCVGenInstrInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "RISCVGenRegisterInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "RISCVGenSubtargetInfo.inc"
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using namespace llvm;
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static MCInstrInfo *createRISCVMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitRISCVMCInstrInfo(X);
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return X;
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}
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static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitRISCVMCRegisterInfo(X, RISCV::X1);
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return X;
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}
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static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT,
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const MCTargetOptions &Options) {
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MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
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MCRegister SP = MRI.getDwarfRegNum(RISCV::X2, true);
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MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, SP, 0);
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MAI->addInitialFrameState(Inst);
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return MAI;
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}
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static MCObjectFileInfo *
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createRISCVMCObjectFileInfo(MCContext &Ctx, bool PIC,
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bool LargeCodeModel = false) {
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MCObjectFileInfo *MOFI = new RISCVMCObjectFileInfo();
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MOFI->initMCObjectFileInfo(Ctx, PIC, LargeCodeModel);
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return MOFI;
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}
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static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
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StringRef CPU, StringRef FS) {
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if (CPU.empty() || CPU == "generic")
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CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32";
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return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
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}
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static MCInstPrinter *createRISCVMCInstPrinter(const Triple &T,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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return new RISCVInstPrinter(MAI, MII, MRI);
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}
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static MCTargetStreamer *
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createRISCVObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
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const Triple &TT = STI.getTargetTriple();
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if (TT.isOSBinFormatELF())
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return new RISCVTargetELFStreamer(S, STI);
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return nullptr;
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}
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static MCTargetStreamer *createRISCVAsmTargetStreamer(MCStreamer &S,
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formatted_raw_ostream &OS,
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MCInstPrinter *InstPrint,
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bool isVerboseAsm) {
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return new RISCVTargetAsmStreamer(S, OS);
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}
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static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) {
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return new RISCVTargetStreamer(S);
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}
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namespace {
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class RISCVMCInstrAnalysis : public MCInstrAnalysis {
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int64_t GPRState[31] = {};
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std::bitset<31> GPRValidMask;
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static bool isGPR(unsigned Reg) {
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return Reg >= RISCV::X0 && Reg <= RISCV::X31;
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}
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static unsigned getRegIndex(unsigned Reg) {
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assert(isGPR(Reg) && Reg != RISCV::X0 && "Invalid GPR reg");
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return Reg - RISCV::X1;
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}
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void setGPRState(unsigned Reg, std::optional<int64_t> Value) {
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if (Reg == RISCV::X0)
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return;
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auto Index = getRegIndex(Reg);
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if (Value) {
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GPRState[Index] = *Value;
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GPRValidMask.set(Index);
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} else {
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GPRValidMask.reset(Index);
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}
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}
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std::optional<int64_t> getGPRState(unsigned Reg) const {
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if (Reg == RISCV::X0)
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return 0;
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auto Index = getRegIndex(Reg);
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if (GPRValidMask.test(Index))
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return GPRState[Index];
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return std::nullopt;
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}
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public:
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explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
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: MCInstrAnalysis(Info) {}
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void resetState() override { GPRValidMask.reset(); }
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void updateState(const MCInst &Inst, uint64_t Addr) override {
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// Terminators mark the end of a basic block which means the sequentially
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// next instruction will be the first of another basic block and the current
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// state will typically not be valid anymore. For calls, we assume all
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// registers may be clobbered by the callee (TODO: should we take the
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// calling convention into account?).
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if (isTerminator(Inst) || isCall(Inst)) {
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resetState();
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return;
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}
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switch (Inst.getOpcode()) {
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default: {
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// Clear the state of all defined registers for instructions that we don't
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// explicitly support.
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auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
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for (unsigned I = 0; I < NumDefs; ++I) {
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auto DefReg = Inst.getOperand(I).getReg();
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if (isGPR(DefReg))
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setGPRState(DefReg, std::nullopt);
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}
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break;
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}
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case RISCV::AUIPC:
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setGPRState(Inst.getOperand(0).getReg(),
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Addr + (Inst.getOperand(1).getImm() << 12));
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break;
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}
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}
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bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
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uint64_t &Target) const override {
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if (isConditionalBranch(Inst)) {
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int64_t Imm;
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if (Size == 2)
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Imm = Inst.getOperand(1).getImm();
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else
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Imm = Inst.getOperand(2).getImm();
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Target = Addr + Imm;
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return true;
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}
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if (Inst.getOpcode() == RISCV::C_JAL || Inst.getOpcode() == RISCV::C_J) {
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Target = Addr + Inst.getOperand(0).getImm();
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return true;
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}
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if (Inst.getOpcode() == RISCV::JAL) {
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Target = Addr + Inst.getOperand(1).getImm();
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return true;
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}
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if (Inst.getOpcode() == RISCV::JALR) {
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if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
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Target = *TargetRegState + Inst.getOperand(2).getImm();
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return true;
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}
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return false;
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}
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return false;
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}
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bool isTerminator(const MCInst &Inst) const override {
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if (MCInstrAnalysis::isTerminator(Inst))
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return true;
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switch (Inst.getOpcode()) {
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default:
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return false;
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case RISCV::JAL:
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case RISCV::JALR:
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return Inst.getOperand(0).getReg() == RISCV::X0;
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}
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}
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bool isCall(const MCInst &Inst) const override {
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if (MCInstrAnalysis::isCall(Inst))
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return true;
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switch (Inst.getOpcode()) {
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default:
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return false;
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case RISCV::JAL:
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case RISCV::JALR:
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return Inst.getOperand(0).getReg() != RISCV::X0;
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}
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}
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bool isReturn(const MCInst &Inst) const override {
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if (MCInstrAnalysis::isReturn(Inst))
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return true;
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switch (Inst.getOpcode()) {
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default:
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return false;
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case RISCV::JALR:
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return Inst.getOperand(0).getReg() == RISCV::X0 &&
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maybeReturnAddress(Inst.getOperand(1).getReg());
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case RISCV::C_JR:
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return maybeReturnAddress(Inst.getOperand(0).getReg());
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}
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}
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bool isBranch(const MCInst &Inst) const override {
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if (MCInstrAnalysis::isBranch(Inst))
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return true;
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return isBranchImpl(Inst);
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}
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bool isUnconditionalBranch(const MCInst &Inst) const override {
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if (MCInstrAnalysis::isUnconditionalBranch(Inst))
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return true;
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return isBranchImpl(Inst);
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}
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bool isIndirectBranch(const MCInst &Inst) const override {
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if (MCInstrAnalysis::isIndirectBranch(Inst))
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return true;
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switch (Inst.getOpcode()) {
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default:
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return false;
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case RISCV::JALR:
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return Inst.getOperand(0).getReg() == RISCV::X0 &&
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!maybeReturnAddress(Inst.getOperand(1).getReg());
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case RISCV::C_JR:
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return !maybeReturnAddress(Inst.getOperand(0).getReg());
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}
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}
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private:
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static bool maybeReturnAddress(unsigned Reg) {
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// X1 is used for normal returns, X5 for returns from outlined functions.
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return Reg == RISCV::X1 || Reg == RISCV::X5;
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}
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static bool isBranchImpl(const MCInst &Inst) {
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switch (Inst.getOpcode()) {
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default:
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return false;
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case RISCV::JAL:
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return Inst.getOperand(0).getReg() == RISCV::X0;
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case RISCV::JALR:
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return Inst.getOperand(0).getReg() == RISCV::X0 &&
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!maybeReturnAddress(Inst.getOperand(1).getReg());
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case RISCV::C_JR:
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return !maybeReturnAddress(Inst.getOperand(0).getReg());
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}
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}
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};
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} // end anonymous namespace
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static MCInstrAnalysis *createRISCVInstrAnalysis(const MCInstrInfo *Info) {
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return new RISCVMCInstrAnalysis(Info);
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}
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namespace {
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MCStreamer *createRISCVELFStreamer(const Triple &T, MCContext &Context,
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std::unique_ptr<MCAsmBackend> &&MAB,
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std::unique_ptr<MCObjectWriter> &&MOW,
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std::unique_ptr<MCCodeEmitter> &&MCE,
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bool RelaxAll) {
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return createRISCVELFStreamer(Context, std::move(MAB), std::move(MOW),
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std::move(MCE), RelaxAll);
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}
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} // end anonymous namespace
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTargetMC() {
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for (Target *T : {&getTheRISCV32Target(), &getTheRISCV64Target()}) {
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TargetRegistry::RegisterMCAsmInfo(*T, createRISCVMCAsmInfo);
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TargetRegistry::RegisterMCObjectFileInfo(*T, createRISCVMCObjectFileInfo);
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TargetRegistry::RegisterMCInstrInfo(*T, createRISCVMCInstrInfo);
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TargetRegistry::RegisterMCRegInfo(*T, createRISCVMCRegisterInfo);
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TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend);
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TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter);
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TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter);
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TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfo);
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TargetRegistry::RegisterELFStreamer(*T, createRISCVELFStreamer);
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TargetRegistry::RegisterObjectTargetStreamer(
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*T, createRISCVObjectTargetStreamer);
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TargetRegistry::RegisterMCInstrAnalysis(*T, createRISCVInstrAnalysis);
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// Register the asm target streamer.
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TargetRegistry::RegisterAsmTargetStreamer(*T, createRISCVAsmTargetStreamer);
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// Register the null target streamer.
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TargetRegistry::RegisterNullTargetStreamer(*T,
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createRISCVNullTargetStreamer);
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}
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}
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