45 lines
2 KiB
TableGen
45 lines
2 KiB
TableGen
//===-- RISCVInstrInfoXVentana.td --------------------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the vendor extensions defined by Ventana Micro Systems.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// XVentanaCondOps
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//===----------------------------------------------------------------------===//
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let Predicates = [IsRV64, HasVendorXVentanaCondOps], hasSideEffects = 0,
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mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, DecoderNamespace = "XVentana" in
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class VTMaskedMove<bits<3> funct3, string opcodestr>
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: RVInstR<0b0000000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
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(ins GPR:$rs1, GPR:$rs2), opcodestr,
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"$rd, $rs1, $rs2"> {
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}
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def VT_MASKC : VTMaskedMove<0b110, "vt.maskc">,
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Sched<[WriteIALU, ReadIALU, ReadIALU]>;
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def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">,
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Sched<[WriteIALU, ReadIALU, ReadIALU]>;
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let Predicates = [IsRV64, HasVendorXVentanaCondOps] in {
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def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
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(VT_MASKC GPR:$rs1, GPR:$rc)>;
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def : Pat<(i64 (riscv_czero_nez GPR:$rs1, GPR:$rc)),
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(VT_MASKCN GPR:$rs1, GPR:$rc)>;
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def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, (riscv_setne (i64 GPR:$rc)))),
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(VT_MASKC GPR:$rs1, GPR:$rc)>;
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def : Pat<(i64 (riscv_czero_eqz GPR:$rs1, (riscv_seteq (i64 GPR:$rc)))),
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(VT_MASKCN GPR:$rs1, GPR:$rc)>;
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def : Pat<(i64 (riscv_czero_nez GPR:$rs1, (riscv_setne (i64 GPR:$rc)))),
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(VT_MASKCN GPR:$rs1, GPR:$rc)>;
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def : Pat<(i64 (riscv_czero_nez GPR:$rs1, (riscv_seteq (i64 GPR:$rc)))),
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(VT_MASKC GPR:$rs1, GPR:$rc)>;
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} // Predicates = [IsRV64, HasVendorXVentanaCondOps]
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