32 lines
1.4 KiB
TableGen
32 lines
1.4 KiB
TableGen
//===-- RISCVInstrInfoZvfbf.td - 'Zvfbf*' instructions -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'Zvfbfmin'
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// extension, providing vector conversion instructions for BFloat16.
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// This version is still experimental as the 'Zvfbfmin' extension hasn't been
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// ratified yet.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZvfbfmin], Constraints = "@earlyclobber $vd",
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mayRaiseFPException = true in {
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let RVVConstraint = WidenCvt in
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defm VFWCVTBF16_F_F_V : VWCVTF_FV_VS2<"vfwcvtbf16.f.f.v", 0b010010, 0b01101>;
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let Uses = [FRM] in
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defm VFNCVTBF16_F_F_W : VNCVTF_FV_VS2<"vfncvtbf16.f.f.w", 0b010010, 0b11101>;
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}
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let Predicates = [HasStdExtZvfbfwma],
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Constraints = "@earlyclobber $vd_wb, $vd = $vd_wb",
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RVVConstraint = WidenV, Uses = [FRM], mayRaiseFPException = true in {
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defm VFWMACCBF16_V : VWMAC_FV_V_F<"vfwmaccbf16", 0b111011>;
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}
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