167 lines
5.4 KiB
YAML
167 lines
5.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: known_sign_bits_smed3_0
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: known_sign_bits_smed3_0
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
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; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -255
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; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 255
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; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
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; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)
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%val:_(s32) = COPY $vgpr0
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%val0:_(s32) = G_SEXT_INREG %val, 8
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%val1:_(s32) = G_CONSTANT i32 -255
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%val2:_(s32) = G_CONSTANT i32 255
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%smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
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%inreg:_(s32) = G_SEXT_INREG %smed3, 9
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$vgpr0 = COPY %inreg
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...
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---
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name: known_sign_bits_smed3_1
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: known_sign_bits_smed3_1
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
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; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -255
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; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 255
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; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val0, %val2
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; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)
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%val:_(s32) = COPY $vgpr0
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%val0:_(s32) = G_SEXT_INREG %val, 8
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%val1:_(s32) = G_CONSTANT i32 -255
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%val2:_(s32) = G_CONSTANT i32 255
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%smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val0, %val2
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%inreg:_(s32) = G_SEXT_INREG %smed3, 9
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$vgpr0 = COPY %inreg
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...
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---
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name: known_sign_bits_smed3_2
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: known_sign_bits_smed3_2
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
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; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -256
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; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 128
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; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val2, %val0
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; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)
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%val:_(s32) = COPY $vgpr0
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%val0:_(s32) = G_SEXT_INREG %val, 8
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%val1:_(s32) = G_CONSTANT i32 -256
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%val2:_(s32) = G_CONSTANT i32 128
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%smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val2, %val0
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%inreg:_(s32) = G_SEXT_INREG %smed3, 9
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$vgpr0 = COPY %inreg
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...
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---
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name: not_enough_sign_bits_smed3_0
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: not_enough_sign_bits_smed3_0
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
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; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 9
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; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9
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; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
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; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8
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; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
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%val:_(s32) = COPY $vgpr0
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%val0:_(s32) = G_SEXT_INREG %val, 8
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%val1:_(s32) = G_SEXT_INREG %val, 9
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%val2:_(s32) = G_SEXT_INREG %val, 9
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%smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
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%inreg:_(s32) = G_SEXT_INREG %smed3, 8
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$vgpr0 = COPY %inreg
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...
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---
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name: not_enough_sign_bits_smed3_1
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: not_enough_sign_bits_smed3_1
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 9
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; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 8
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; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9
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; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
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; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8
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; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
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%val:_(s32) = COPY $vgpr0
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%val0:_(s32) = G_SEXT_INREG %val, 9
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%val1:_(s32) = G_SEXT_INREG %val, 8
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%val2:_(s32) = G_SEXT_INREG %val, 9
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%smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
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%inreg:_(s32) = G_SEXT_INREG %smed3, 8
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$vgpr0 = COPY %inreg
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...
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---
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name: not_enough_sign_bits_smed3_2
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-LABEL: name: not_enough_sign_bits_smed3_2
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
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; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 8
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; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9
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; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
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; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8
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; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
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%val:_(s32) = COPY $vgpr0
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%val0:_(s32) = G_SEXT_INREG %val, 8
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%val1:_(s32) = G_SEXT_INREG %val, 8
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%val2:_(s32) = G_SEXT_INREG %val, 9
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%smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
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%inreg:_(s32) = G_SEXT_INREG %smed3, 8
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$vgpr0 = COPY %inreg
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...
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