98 lines
2.9 KiB
LLVM
98 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
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declare <16 x i16> @llvm.loongarch.lasx.xvexth.h.b(<32 x i8>)
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define <16 x i16> @lasx_xvexth_h_b(<32 x i8> %va) nounwind {
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; CHECK-LABEL: lasx_xvexth_h_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvexth.h.b $xr0, $xr0
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i16> @llvm.loongarch.lasx.xvexth.h.b(<32 x i8> %va)
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ret <16 x i16> %res
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}
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declare <8 x i32> @llvm.loongarch.lasx.xvexth.w.h(<16 x i16>)
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define <8 x i32> @lasx_xvexth_w_h(<16 x i16> %va) nounwind {
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; CHECK-LABEL: lasx_xvexth_w_h:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvexth.w.h $xr0, $xr0
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i32> @llvm.loongarch.lasx.xvexth.w.h(<16 x i16> %va)
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ret <8 x i32> %res
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}
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declare <4 x i64> @llvm.loongarch.lasx.xvexth.d.w(<8 x i32>)
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define <4 x i64> @lasx_xvexth_d_w(<8 x i32> %va) nounwind {
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; CHECK-LABEL: lasx_xvexth_d_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvexth.d.w $xr0, $xr0
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i64> @llvm.loongarch.lasx.xvexth.d.w(<8 x i32> %va)
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.loongarch.lasx.xvexth.q.d(<4 x i64>)
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define <4 x i64> @lasx_xvexth_q_d(<4 x i64> %va) nounwind {
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; CHECK-LABEL: lasx_xvexth_q_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvexth.q.d $xr0, $xr0
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i64> @llvm.loongarch.lasx.xvexth.q.d(<4 x i64> %va)
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ret <4 x i64> %res
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}
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declare <16 x i16> @llvm.loongarch.lasx.xvexth.hu.bu(<32 x i8>)
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define <16 x i16> @lasx_xvexth_hu_bu(<32 x i8> %va) nounwind {
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; CHECK-LABEL: lasx_xvexth_hu_bu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvexth.hu.bu $xr0, $xr0
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; CHECK-NEXT: ret
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entry:
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%res = call <16 x i16> @llvm.loongarch.lasx.xvexth.hu.bu(<32 x i8> %va)
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ret <16 x i16> %res
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}
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declare <8 x i32> @llvm.loongarch.lasx.xvexth.wu.hu(<16 x i16>)
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define <8 x i32> @lasx_xvexth_wu_hu(<16 x i16> %va) nounwind {
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; CHECK-LABEL: lasx_xvexth_wu_hu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvexth.wu.hu $xr0, $xr0
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; CHECK-NEXT: ret
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entry:
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%res = call <8 x i32> @llvm.loongarch.lasx.xvexth.wu.hu(<16 x i16> %va)
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ret <8 x i32> %res
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}
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declare <4 x i64> @llvm.loongarch.lasx.xvexth.du.wu(<8 x i32>)
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define <4 x i64> @lasx_xvexth_du_wu(<8 x i32> %va) nounwind {
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; CHECK-LABEL: lasx_xvexth_du_wu:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvexth.du.wu $xr0, $xr0
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i64> @llvm.loongarch.lasx.xvexth.du.wu(<8 x i32> %va)
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ret <4 x i64> %res
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}
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declare <4 x i64> @llvm.loongarch.lasx.xvexth.qu.du(<4 x i64>)
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define <4 x i64> @lasx_xvexth_qu_du(<4 x i64> %va) nounwind {
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; CHECK-LABEL: lasx_xvexth_qu_du:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xvexth.qu.du $xr0, $xr0
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; CHECK-NEXT: ret
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entry:
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%res = call <4 x i64> @llvm.loongarch.lasx.xvexth.qu.du(<4 x i64> %va)
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ret <4 x i64> %res
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}
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